Commit Graph

336 Commits

Author SHA1 Message Date
AurelienUoU 317c3b59c9 Update go.sh and upload pip_add.v 2018-12-11 15:47:05 -07:00
AurelienUoU fb0992bd85 Update go.sh and Makefile 2018-12-11 15:31:32 -07:00
AurelienUoU c2c4e78639 Add pip_add benchmark 2018-12-11 15:29:48 -07:00
AurelienUoU f5ea3ff233 Add an autochecked configuration free testbench 2018-12-11 14:44:13 -07:00
tangxifan 72fbd8d6a8 update blif reader to identify clock signals 2018-12-10 13:28:44 -07:00
AurelienUoU a69c2e1882 Add security in checking to avoid simulation glitch error 2018-12-10 09:46:16 -07:00
AurelienUoU 7020d9b4b6 Edit waveform generator + fix clock mapping in autochecked testbench 2018-12-09 15:48:59 -07:00
AurelienUoU 5e94b7093d Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench) 2018-12-08 22:57:54 -07:00
Aur??Lien ALACCHI 10866d1852 Correct verilog syntax error in autocheck testbench 2018-12-08 17:40:23 -07:00
Aur??Lien ALACCHI d716b67e23 Correct syntax error in autocheck testbench 2018-12-08 17:29:56 -07:00
Aur??Lien ALACCHI 0580d8243f Add Autochek testbench option 2018-12-08 17:19:12 -07:00
Baudouin Chauviere 79930982cf Changed for the naming 2018-12-08 16:19:38 -07:00
Baudouin Chauviere 4440066565 added the script to launch vpr with picorv 2018-12-08 16:01:58 -07:00
Baudouin Chauviere c130404158 add a section for picorv generation through the flow 2018-12-08 11:33:14 -07:00
Aur??Lien ALACCHI 4cc875a5a5 fix a bug in wired LUT 2018-12-06 18:00:17 -07:00
tangxifan b3c1018e28 fixed a bug in wired LUT 2018-12-06 16:50:30 -07:00
Aur??Lien ALACCHI eebdf7cb10 Add possibility to choose default value for initialization 2018-12-06 15:34:14 -07:00
Baudouin Chauviere b6bb419e1d add a ModelSim option 2018-12-06 14:13:37 -07:00
Baudouin Chauviere fe47b3d21f Changing arch from memory dec to scff. Get the bitstream from go.sh 2018-12-06 14:03:17 -07:00
Aur??Lien ALACCHI 8281b7346b Edit auto-generated modelsim script 2018-12-05 16:15:29 -07:00
Aur??Lien ALACCHI 44b7f7f3d4 Correct sub_modules.v generation to include decoders.v when necessary 2018-12-05 13:52:25 -07:00
Aur??Lien ALACCHI dc4accedd9 Add forgottent files + add parameter transmission from verilog_api.c 2018-12-05 11:33:14 -07:00
Aur??Lien ALACCHI 9a8c7b391a Add process for modelsim script autogeneration 2018-12-05 09:20:47 -07:00
Aur??Lien ALACCHI 75d64db0f9 Add verilog header sub_module.v file generation 2018-12-04 18:42:47 -07:00
Aur??Lien ALACCHI 8ac566ecc0 Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
tangxifan 70751551b5 fix a bug in wired LUT support 2018-11-30 21:33:31 -07:00
tangxifan e223868df8 fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
Aur??Lien ALACCHI de2bc18bbb bugs fixed for shift register benchmark 2018-11-26 16:58:45 -07:00
Baudouin Chauviere 9611576d6a Update on the examples to respect the new syntax 2018-11-19 15:50:29 -07:00
tangxifan 861c449606 support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
Baudouin Chauviere f7d7a056da Modification of the fpga_spice_utils 2018-11-15 14:11:55 -07:00
Baudouin Chauviere c81d00bb51 Correction of the double free bug 2018-11-15 13:55:16 -07:00
tangxifan c67ba5f58a clean up codes 2018-09-27 14:26:08 -06:00
Baudouin Chauviere 31c3eba111 ReadMe modifications to add the beginning of the FPGA-SPICE tutorial
Modifications on the addresses aswell and the different commands when they were not working.
To do still:
-create a script to change the addresses when needed
-continue the tutorial
2018-09-27 09:33:39 -06:00
tangxifan 681cca99a4 fix a bug in tapbuf 2018-09-21 19:00:22 -06:00
tangxifan d683134b12 rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00