2 Commits

Author	SHA1	Message	Date
tangxifan	2fbf9c2cfc	change to a higher simulation clock speed to accelerate CI verification. ... Later, we should place simulation information in another XML so that we can reuse that easily	2020-06-11 19:31:03 -06:00
tangxifan	2ffd174e6a	fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI	2020-04-15 15:48:33 -06:00