Ganesh Gore
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e845b62322
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Update regession tasks
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2022-05-05 01:46:19 -06:00 |
Lalit Sharma
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ea4aee8cb2
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For time-being yosys script running in no_adder mode.
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2021-02-28 22:07:23 -08:00 |
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Lalit Sharma
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d842026672
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Disabling verilog testbench generation for quicklogic tests
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2021-02-21 21:58:23 -08:00 |
Tarachand Pagarani
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426b6449d8
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change the test to turn off power analysis
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2021-02-15 02:45:38 -08:00 |
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Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |