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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 4aa6264b1c [Tool] Rework simulation time period to be sync with actual stimuli 2020-12-02 22:58:13 -07:00
tangxifan bb671acac3 add formal random Verilog testbench generation 2020-02-26 20:58:16 -07:00