tangxifan
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73e2b857a3
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add buffer support to FPGA-SPICE
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2020-07-24 15:54:18 -06:00 |
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tangxifan
|
2603836111
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split logical tile netlists to keep good Verilog hierarchy
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2020-07-24 12:53:21 -06:00 |
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tangxifan
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be5966475e
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formulate file name, module name and instance name to be consistent
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2020-07-24 12:23:27 -06:00 |
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tangxifan
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22159531c5
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bug fix in power gating support of FPGA-Verilog
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2020-07-22 20:21:38 -06:00 |
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tangxifan
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a4a38f8156
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support multi-bit power gate ports in FPGA-SPICE
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2020-07-22 20:04:39 -06:00 |
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tangxifan
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f573fa3ee0
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move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
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2020-07-22 18:47:12 -06:00 |
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tangxifan
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97cca72590
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add spice support on power gated inverters
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2020-07-22 18:21:11 -06:00 |
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tangxifan
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b5fd6aa859
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add inverter subckt writer to FPGA-SPICE
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2020-07-17 13:01:08 -06:00 |
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tangxifan
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eb070694b5
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fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
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2020-07-15 17:52:41 -06:00 |
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tangxifan
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66a50742fc
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use configuration chain in the k4k4 test case to speed up CI
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2020-07-15 11:56:11 -06:00 |
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tangxifan
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3f14fe62c7
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add fast configuration support for configuration chain protocol
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2020-07-15 11:44:23 -06:00 |
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tangxifan
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1b55dfb441
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hotfix on treating the dangling ports in pb_graph for analysis SDC generator
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2020-07-09 23:28:42 -06:00 |
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tangxifan
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62fd0947f5
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using a unified string to replace multi net names to save memory of bitstream database
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2020-07-08 16:28:20 -06:00 |
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tangxifan
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66e5e141a1
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improve fabric key loader to reduce runtime
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2020-07-07 10:19:34 -06:00 |
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tangxifan
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824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
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2020-07-06 16:42:33 -06:00 |
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tangxifan
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462fc0d04e
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add spice transistor wrapper writer
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2020-07-05 14:50:29 -06:00 |
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tangxifan
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b38ee0e8be
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add spice writer functions
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2020-07-05 13:58:05 -06:00 |
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tangxifan
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81171a8f97
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start transplanting FPGA-SPICE
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2020-07-05 12:10:12 -06:00 |
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tangxifan
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1ad6e8292a
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move constants from verilog domain to common so that FPGA-SPICE can share
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2020-07-05 11:39:46 -06:00 |
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tangxifan
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7c2a0a6ad2
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streamline fabric verilog options
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2020-07-05 11:28:14 -06:00 |
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tangxifan
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83e26adf90
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add module usage types for future FPGA-SPICE development
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2020-07-04 22:33:54 -06:00 |
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tangxifan
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4f8260a7ba
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remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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tangxifan
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033c92c365
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precisely reserve memory for child blocks in bitstream manager
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2020-07-03 22:47:21 -06:00 |
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tangxifan
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46f038c829
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bug fix in grid config block allocation
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2020-07-03 20:46:04 -06:00 |
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tangxifan
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f040fc78a9
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now reserve blocks in bitstream manager can accurately capture the size
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2020-07-03 20:06:12 -06:00 |
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tangxifan
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8067a13346
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bug fix for memory bank due to encoding bl/wl addresses in fabric bitstream
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2020-07-03 15:56:20 -06:00 |
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tangxifan
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2a9377b3f4
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use encoded address in storage of fabric bitstream to save memory
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2020-07-03 15:12:29 -06:00 |
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tangxifan
|
1f38e17111
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bug fix for naming conflicts in mux local encoder and architecture decoders
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2020-07-03 14:12:13 -06:00 |
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tangxifan
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70d9678578
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reserve child block in bistream manager
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2020-07-03 14:04:10 -06:00 |
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tangxifan
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2783fda344
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use index range instead of vector for block bitstream
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2020-07-03 11:42:38 -06:00 |
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tangxifan
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6ea857ae6c
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use fast method to inquire number of bits and blocks in bitstream databases
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2020-07-03 10:55:25 -06:00 |
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tangxifan
|
7ca1a5bdc1
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Fabric bitstream now allocates vectors in conditions for memory efficiency
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2020-07-03 10:17:03 -06:00 |
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tangxifan
|
8a45e48a1c
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minor fix
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2020-07-02 22:27:48 -06:00 |
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tangxifan
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246b4d5ac6
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reserve block bits to save memory
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2020-07-02 21:52:32 -06:00 |
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tangxifan
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dee4be96af
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reserve all the input/output net storage in bitstream manager
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2020-07-02 19:17:34 -06:00 |
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tangxifan
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f97e3bfba6
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add timer to openfpga shell
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2020-07-02 18:02:33 -06:00 |
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tangxifan
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81c9fcb7c0
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bug fix when optimizing the fabric bitstream data structure
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2020-07-02 16:41:32 -06:00 |
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tangxifan
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adee87569d
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enable fast bitstream building by creating a frame view of fabric
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2020-07-02 16:25:36 -06:00 |
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tangxifan
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9608cefa86
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remove id vector in fabric bitstream database and replace with more memory efficient implementation
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2020-07-02 16:08:50 -06:00 |
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tangxifan
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9f19c36a89
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use char in fabric bitstream to save memory footprint
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2020-07-02 15:56:50 -06:00 |
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tangxifan
|
405824081b
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reserve configuration blocks and bits in bitstream manager builder to be memory efficient
|
2020-07-02 15:28:52 -06:00 |
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tangxifan
|
b85af57971
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optimizing fabric bitsteream memory footprint
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2020-07-02 12:39:18 -06:00 |
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tangxifan
|
ac22ba28e4
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add config protocol type information to simulation ini file
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2020-07-02 12:26:59 -06:00 |
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tangxifan
|
81ecfa3197
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add comments to clarify how to select CB ports when connecting to SBs at the top level
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2020-07-01 14:44:40 -06:00 |
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tangxifan
|
0a3c746fb1
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now split CB module bus ports into lower/upper parts
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2020-07-01 14:37:13 -06:00 |
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tangxifan
|
cb2baed257
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bug fix in simulation ini GPIO width
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2020-07-01 13:39:12 -06:00 |
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tangxifan
|
b74dde919d
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add additional information in the simulation ini file for UVM
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2020-07-01 13:07:39 -06:00 |
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tangxifan
|
e688ca1388
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update fabric bitstream writer to support various configuration protocols
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2020-07-01 11:54:28 -06:00 |
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tangxifan
|
1015880d0e
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use easy-to-access net look up in switch block module builder
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2020-06-30 18:15:41 -06:00 |
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tangxifan
|
05187f8aa4
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use typedef to short the module pin information
|
2020-06-30 18:07:22 -06:00 |