tangxifan
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73da4a1d6e
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rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation
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2020-03-09 10:32:03 -06:00 |
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tangxifan
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f821e60405
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clean up deadlinks in doc
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2020-03-09 10:15:16 -06:00 |
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tangxifan
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1f092171f2
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Merge branch 'refactoring' into dev
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2020-03-09 09:45:31 -06:00 |
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tangxifan
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d61ae5561b
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start cleanup the documentation for openfpga shell
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2020-03-09 09:44:19 -06:00 |
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tangxifan
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94d9b6e615
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Merge branch 'refactoring' into dev
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2020-03-09 09:35:59 -06:00 |
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tangxifan
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3aca7b498c
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Show help desk when a command is called inside shell without satisfying the dependency
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2020-03-09 09:34:21 -06:00 |
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tangxifan
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2f38b5cbc2
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Merge branch 'refactoring' into dev
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2020-03-08 16:23:20 -06:00 |
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tangxifan
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aff73bdd74
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deployed edge sorting and make it as an option to link_arch command
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2020-03-08 15:59:53 -06:00 |
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tangxifan
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b80e26e711
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update bitstream generator to use sorted edges
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2020-03-08 15:36:47 -06:00 |
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tangxifan
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5558932762
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use sorted edges in building routing modules
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2020-03-08 15:31:41 -06:00 |
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tangxifan
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7a7f8374b3
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start deploying edge sorting in uniquifying SB modules
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2020-03-08 15:24:34 -06:00 |
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tangxifan
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f9499afe04
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remove unused variable
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2020-03-08 15:00:01 -06:00 |
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tangxifan
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0c7aa2581d
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update vpr8 version with hotfix on undriven pins in GSB
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2020-03-08 14:58:56 -06:00 |
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tangxifan
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b219b096ee
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hotfix on removing dangling inputs from GSB, which are CLB direct output
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2020-03-08 13:54:49 -06:00 |
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tangxifan
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b2534f1a09
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Merge branch 'refactoring' into dev
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2020-03-07 23:31:45 -07:00 |
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tangxifan
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0fbf3fca41
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start developing edge sorting inside RRGSB
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2020-03-07 23:30:55 -07:00 |
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tangxifan
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8b40ca2990
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Merge branch 'refactoring' into dev
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2020-03-07 17:54:13 -07:00 |
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tangxifan
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ca92c2717f
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bug fix for tile directs
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2020-03-07 16:00:32 -07:00 |
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tangxifan
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e48c2b116d
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bug fixing for duplicated grid pin names
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2020-03-07 15:46:12 -07:00 |
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tangxifan
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37423729ec
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bug fixing for naming the duplicated pins
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2020-03-07 15:44:57 -07:00 |
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tangxifan
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3eeac94a6e
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Merge branch 'refactoring' into dev
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2020-03-06 20:58:07 -07:00 |
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tangxifan
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c36c302052
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looks like tileable routing is working
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2020-03-06 17:16:53 -07:00 |
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tangxifan
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f54f46483b
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start debugging tileable rr_graph generator
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2020-03-06 17:02:22 -07:00 |
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tangxifan
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5be118d695
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tileable rr_graph builder ready to debug
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2020-03-06 16:18:45 -07:00 |
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tangxifan
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245a379c4f
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start plug in tileable rr_graph builder
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2020-03-06 16:03:00 -07:00 |
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tangxifan
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3eb59d201f
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adapt top function of tileable rr_graph builder
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2020-03-06 15:24:26 -07:00 |
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tangxifan
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441a307100
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add routing chan width corrector to rr_graph builder utils
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2020-03-06 14:54:40 -07:00 |
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tangxifan
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441de12936
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adapt Fc in gsb connection builder to use VPR8 Fc builder
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2020-03-06 14:43:12 -07:00 |
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tangxifan
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ee4d5e46a0
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Merge branch 'refactoring' into dev
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2020-03-05 21:25:36 -07:00 |
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tangxifan
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8d350ee22f
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adapt tileable rr_graph edge builder to rr_graph object
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2020-03-05 20:50:21 -07:00 |
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tangxifan
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328488f357
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adapt chan rr node builder to use rr_graph obj
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2020-03-05 20:15:16 -07:00 |
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tangxifan
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3e3a523926
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Merge branch 'refactoring' into dev
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2020-03-05 17:48:43 -07:00 |
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tangxifan
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5067dd846e
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adapting channel rr_node builder for tileable rr_graph
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2020-03-05 17:47:48 -07:00 |
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tangxifan
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850788eace
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adapt tileable rr_graph node builder for rr_graph object
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2020-03-05 17:15:49 -07:00 |
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tangxifan
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5dcffb1a6e
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Merge branch 'refactoring' into dev
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2020-03-05 15:36:16 -07:00 |
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tangxifan
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de62ce8872
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add node builder for tileable rr_graph builder
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2020-03-05 15:34:04 -07:00 |
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tangxifan
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646ee90937
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bring tileable gsb builder for rr_graph online
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2020-03-04 18:19:53 -07:00 |
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tangxifan
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4455615980
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adapt tileable routing channel detail builder
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2020-03-04 14:21:35 -07:00 |
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tangxifan
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6e83154703
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move rr_gsb and rr_chan to tileable rr_graph builder
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2020-03-04 14:14:28 -07:00 |
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tangxifan
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4b7d2221d1
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adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr
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2020-03-04 13:55:53 -07:00 |
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tangxifan
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524798799c
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start adapting tileable rr_graph builder. Bring channel node detail data structure online
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2020-03-04 11:21:34 -07:00 |
AurelienUoU
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aed3b01800
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Directlist extension bug fix
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2020-03-04 09:09:06 -07:00 |
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tangxifan
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9f13d3bc23
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Merge branch 'refactoring' into dev
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2020-03-03 12:31:20 -07:00 |
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tangxifan
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7fcd27e000
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now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
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2020-03-03 12:29:58 -07:00 |
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tangxifan
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3241d8bd37
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put analysis sdc writer online. Minor bug in redudant '/' to be fixed
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2020-03-02 19:54:18 -07:00 |
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tangxifan
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037c7e5c43
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adapt top-level function for analysis SDC writer
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2020-03-02 17:58:44 -07:00 |
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tangxifan
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24f7416c71
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adapt analysis SDC writer for grids
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2020-03-02 17:15:01 -07:00 |
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tangxifan
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6474183539
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adapt analysis SDC writer for routing modules
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2020-03-02 14:29:58 -07:00 |
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tangxifan
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543cff58b9
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start porting analysis SDC writer
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2020-03-02 13:44:08 -07:00 |
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tangxifan
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7befcaba57
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Merge branch 'refactoring' into dev
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2020-03-02 11:22:58 -07:00 |