4 Commits

Author	SHA1	Message	Date
tangxifan	29104b6fa5	rework on the circuit model ports and start prototyping mux Verilog generation	2019-08-20 15:24:53 -06:00
tangxifan	003883b13b	implementing the local encoders	2019-08-06 14:17:55 -06:00
Baudouin Chauviere	332ce17f03	Division between horizontal and vertical analysis	2019-06-25 13:44:41 -06:00
tangxifan	46d44fa42a	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00