tangxifan
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711e369fe7
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fixing bugs in the SDC generator and report_timing
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2019-06-26 18:09:09 -06:00 |
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tangxifan
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d50fb7ee19
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
Baudouin Chauviere
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332ce17f03
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Division between horizontal and vertical analysis
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2019-06-25 13:44:41 -06:00 |
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tangxifan
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8a8f4153ce
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use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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2019-06-10 12:50:10 -06:00 |
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tangxifan
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e31407f693
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start cleaning up SDC generator with new RRGSB data structure
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2019-06-10 10:57:26 -06:00 |
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tangxifan
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17bc7fc296
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update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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2019-06-08 20:11:22 -06:00 |
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tangxifan
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472aff5acb
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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tangxifan
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ce9fc5696c
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
AurelienUoU
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84fabbd43b
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Fix sdc analysis bug related to virtual nodes + add the option in regression test
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2019-06-05 12:10:28 -06:00 |
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Baudouin Chauviere
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d24488092d
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Fix bug
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2019-06-05 11:40:04 -06:00 |
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Baudouin Chauviere
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1932d00309
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Correction of the SDC to remove global clocks
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2019-05-30 15:04:21 -06:00 |
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Baudouin Chauviere
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3da216f297
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correction Null issue for the flat model
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2019-05-28 14:15:24 -06:00 |
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tangxifan
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1ade1f1d3f
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update SDC generator disabled_unused_mux by using RRSwitchBlock
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2019-05-24 15:42:00 -06:00 |
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tangxifan
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f27b88db8d
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Use RRChan in SDC generator to replace old data structures
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2019-05-24 15:34:56 -06:00 |
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tangxifan
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924136e7a2
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Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
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2019-05-24 15:10:08 -06:00 |
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Baudouin Chauviere
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2019840d7c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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tangxifan
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c46c0fc97d
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bug fixing for SDC generator
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2019-04-26 14:07:44 -06:00 |
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tangxifan
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46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |