3 Commits

Author	SHA1	Message	Date
tangxifan	84edd41342	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
tangxifan	dba48fb171	[test] reworking adder mapping flow to validate carry chain mapping	2023-06-20 16:57:08 -07:00
tangxifan	cea43c2c45	[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage	2021-03-16 18:04:31 -06:00