5 Commits

Author	SHA1	Message	Date
tangxifan	965ee2190e	[core] support intermediate driver in clock arch	2024-09-20 17:42:26 -07:00
tangxifan	b2fc47a12a	[core] reworked i/o for clock network files	2024-07-10 14:34:54 -07:00
tangxifan	34fb003911	[core] replace width syntax with global port name	2024-06-29 10:46:00 -07:00
tangxifan	cab649893b	[core] update clock architecture	2024-06-26 18:06:39 -07:00
tangxifan	36ef555dda	[lib] add example arch for clock arch with internal drivers	2024-06-24 18:33:47 -07:00