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OpenFPGA
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1353 Commits

Author SHA1 Message Date
BaudouinChauviere 88af64c606
Update eda_flow.rst 
Distributions compilable added
 2018-12-05 16:29:07 -07:00
BaudouinChauviere d0ac931daa
Update README.md 
Small correction
 2018-12-05 16:27:37 -07:00
BaudouinChauviere 576feb600f
Update eda_flow.rst 
Completed with FPGA-Verilog/Bitstream and corrected few errors
 2018-12-05 16:24:03 -07:00
Aur??Lien ALACCHI 8281b7346b Edit auto-generated modelsim script 2018-12-05 16:15:29 -07:00
Aur??Lien ALACCHI 44b7f7f3d4 Correct sub_modules.v generation to include decoders.v when necessary 2018-12-05 13:52:25 -07:00
Aur??Lien ALACCHI dc4accedd9 Add forgottent files + add parameter transmission from verilog_api.c 2018-12-05 11:33:14 -07:00
Aur??Lien ALACCHI 9a8c7b391a Add process for modelsim script autogeneration 2018-12-05 09:20:47 -07:00
Aur??Lien ALACCHI 75d64db0f9 Add verilog header sub_module.v file generation 2018-12-04 18:42:47 -07:00
Aur??Lien ALACCHI 8ac566ecc0 Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
BaudouinChauviere 0f87fb9c3f
Update file_organization.rst 
Correction on the routing
 2018-12-03 14:21:40 -07:00
BaudouinChauviere e541834bd0
Update file_organization.rst 
Made similar to the SPICE one
 2018-12-03 14:20:34 -07:00
BaudouinChauviere cd301a5bb8
Update file_organization.rst 
Correction of the hierarchy
 2018-12-03 14:09:11 -07:00
BaudouinChauviere 9c97125b0d
Update spice_simulation.rst 
typo
 2018-12-03 13:42:45 -07:00
BaudouinChauviere b8f702e16d
Update file_organization.rst 
Creation of the table for better understanding
 2018-12-03 13:40:42 -07:00
BaudouinChauviere 10cbd2efef
Update index.rst 
Commenting the multi mode out until more mature
 2018-12-03 11:50:13 -07:00
BaudouinChauviere 8e7def7f88
Update link_circuit_modules.rst 
Correction of typos
 2018-12-03 11:39:44 -07:00
BaudouinChauviere f8e801b9d1
Merge pull request #1 from LNIS-Projects/Documentation-Update 
Update index.rst
 2018-12-03 11:27:05 -07:00
BaudouinChauviere a4d29aeb1b
Update circuit_model_examples.rst 
Typo correction
 2018-12-03 11:26:04 -07:00
BaudouinChauviere e39e0219e9
Update circuit_modules.rst 
Move the examples from this part to their own
 2018-12-03 10:59:20 -07:00
BaudouinChauviere 7a49ca8ce2
Update index.rst 
New section in the doc
 2018-12-03 10:58:50 -07:00
BaudouinChauviere 99769c1510
Create circuit_model_examples.rst 
Better architecture of the doc
 2018-12-03 10:58:11 -07:00
BaudouinChauviere 47a214520f
Update index.rst 
Skip lines
 2018-12-03 10:32:15 -07:00
BaudouinChauviere 6827549be2
Update index.rst 
Include the links for the external documentation
 2018-12-03 10:31:02 -07:00
tangxifan 70751551b5 fix a bug in wired LUT support 2018-11-30 21:33:31 -07:00
tangxifan 4f5f8de46f Add Yosys and update flow_flow Perl Script 2018-11-30 21:14:43 -07:00
tangxifan e223868df8 fix bugs for wired LUTs 2018-11-27 12:46:30 -07:00
Aur??Lien ALACCHI de2bc18bbb bugs fixed for shift register benchmark 2018-11-26 16:58:45 -07:00
Baudouin Chauviere d55ecd154b Add the PTM to the benchmark flow 2018-11-21 11:32:34 -07:00
Baudouin Chauviere 8ce0a84bc1 Correction of the global make, the fpga_flow and the doc 2018-11-20 14:47:15 -07:00
Baudouin Chauviere 03e902023a Perl script integrated to flow. rm shell one 2018-11-20 13:32:11 -07:00
Baudouin Chauviere 15d69e2bb1 Generation script finished TODO: integration in flow 2018-11-20 13:24:31 -07:00
Baudouin Chauviere e74f05a161 Switching from sh to pl 2018-11-20 10:15:31 -07:00
Baudouin Chauviere 9611576d6a Update on the examples to respect the new syntax 2018-11-19 15:50:29 -07:00
tangxifan 861c449606 support wired LUT in FPGA-SPICE and FPGA-Verilog 2018-11-15 15:57:49 -07:00
Baudouin Chauviere f7d7a056da Modification of the fpga_spice_utils 2018-11-15 14:11:55 -07:00
Baudouin Chauviere c81d00bb51 Correction of the double free bug 2018-11-15 13:55:16 -07:00
Baudouin Chauviere e93c96801b Adding abc without bb support in the project 
Needed for fpga_flow in standard mode (vtr_standard uses abc with bb support)
 2018-11-15 13:51:25 -07:00
Baudouin Chauviere ea9cb91cad Update of the examples to correspond to the new syntax 2018-11-14 14:01:39 -07:00
Baudouin Chauviere ebc4629946 Correction of the compilation to automatically get the submodules 2018-11-08 15:56:22 -07:00
Baudouin Chauviere fbaa52544c Implementation of OpenSTA in the project 2018-11-08 13:13:45 -07:00
Baudouin Chauviere dddca8acbb Global Makefile and typo correction 2018-10-24 17:34:51 -06:00
Baudouin Chauviere 9538dbd644 Config script written and changed some rights for some files 2018-10-24 15:59:32 -06:00
Aurelien Alacchi 4a950c6857 Flatten_hierarchy_doc 2018-10-18 16:28:12 -06:00
Aurelien Alacchi aa5449c37d Verif_modif_doc_title_2 2018-10-17 16:49:55 -06:00
Aurelien Alacchi 6327a4486b Revert "Verif_modif_doc_title" 
This reverts commit 8f7f88ebea.
 2018-10-17 16:47:32 -06:00
Aurelien Alacchi 8f7f88ebea Verif_modif_doc_title 2018-10-17 16:45:42 -06:00
Aurelien Alacchi 2cfbe2b997 FPGA-Verilog_doc_update 2018-10-17 16:38:03 -06:00
Aurelien Alacchi e96c6e2f02 Revert "Bug_correction_fpga-spice_commandLine" 
This reverts commit 33e76d0255.
 2018-10-12 16:09:14 -06:00
Aurelien Alacchi 33e76d0255 Bug_correction_fpga-spice_commandLine 2018-10-12 16:05:53 -06:00
Aurelien Alacchi 26538cb2bc Correction_file_commandline_fpga-spice 2018-10-12 16:03:23 -06:00