tangxifan
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73386dd1a9
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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tangxifan
|
0daf170e45
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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tangxifan
|
4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
|
0e620f35a4
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bug fixed for MUX2 std cells, avoid duplicated module writing
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2019-11-06 11:45:28 -07:00 |
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tangxifan
|
a308a13d7c
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
|
9cf8683acd
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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tangxifan
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b2f57ecf81
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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tangxifan
|
433fc73460
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refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
|
4da5035627
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Connect CCFFs in a chain in a Verilog module
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2019-09-27 20:50:12 -06:00 |
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tangxifan
|
1e187f3d15
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
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tangxifan
|
56f40cf46c
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light modification on Verilog Mux generation and start refactoring memory Verilog generation
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2019-09-13 12:22:57 -06:00 |
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tangxifan
|
79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
|
6a5b50facf
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refactored RRAM MUX verilog generation
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2019-09-10 20:45:44 -06:00 |
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tangxifan
|
62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
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tangxifan
|
59edd49862
|
refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
|
bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
|
e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
|
fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
|
b6bb433edc
|
bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
|
4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
|
d2d750a15c
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debugged rram mux branch Verilog generation
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2019-09-02 16:21:29 -06:00 |
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tangxifan
|
395bf4fbdf
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refactored rram mux generation
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2019-09-02 14:30:18 -06:00 |
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tangxifan
|
f04565386f
|
refactored behavioral mux branch verilog generation
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2019-08-27 18:39:25 -06:00 |
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tangxifan
|
ab6f1a5461
|
add mux output ids for mux_graph
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2019-08-26 21:21:50 -06:00 |
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tangxifan
|
c43fabb43c
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 10:31:45 -06:00 |
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tangxifan
|
fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
|
63f40f48fa
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
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tangxifan
|
39853408dd
|
add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
|
37a092e885
|
add recursive global port searching for circuit library
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2019-08-23 16:36:30 -06:00 |
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tangxifan
|
7b0c55ce15
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try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
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2019-08-21 22:45:48 -06:00 |
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tangxifan
|
9c43b1b753
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complete refacotriing the inv and buf part in submodules
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2019-08-21 14:54:05 -06:00 |
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tangxifan
|
a40e5c91ca
|
refactored power-gate inverter
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2019-08-20 21:56:55 -06:00 |
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tangxifan
|
19472ace4e
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renaming files
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2019-08-20 21:01:38 -06:00 |