Commit Graph

16 Commits

Author SHA1 Message Date
tangxifan db503ffebf add openfpga read xml executable and start min unit test 2020-01-13 21:05:58 -07:00
tangxifan 48ecb6e48b immigrate XML parser for circuit_lib to library readarchopenfpga 2020-01-12 18:11:00 -07:00
tangxifan 0740684567 remove libs from cache list 2020-01-03 22:06:40 -05:00
tangxifan b728773159 add vtr assert level and copy missing cmake modules from vtr project 2020-01-03 21:56:15 -05:00
tangxifan 670642ee42 add executable to vpr8 directory 2020-01-03 16:50:29 -07:00
tangxifan 0f012a32a5 add vpr8 to cmake compilation 2020-01-03 16:45:31 -07:00
tangxifan f1bafffa87 add vpr8 libs and core engine for further integration 2020-01-03 16:14:42 -07:00
tangxifan e9ed64c926 try to let cmake identify libini 2019-11-01 21:17:35 -06:00
tangxifan 5e156dc725 minor fix for OSX and update travis using ccache to speed up compilation 2019-08-21 15:25:36 -06:00
tangxifan 44d21ebb90 fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
tangxifan ea8c36ce6e upgrade Verilog SB generator using the RRSwitchBlock 2019-05-23 17:37:39 -06:00
AurelienUoU f940c4fd59 Third try to fix issues with graphics on mac 2019-05-15 13:22:14 -06:00
AurelienUoU 41dc359b50 Remove graphics on MacOS -> X11 deprecated and cannot be found by travis 2019-05-15 10:39:20 -06:00
tangxifan e305e60ee4 minor fix on the shell interface of VPR 2019-05-08 14:29:58 -06:00
tangxifan 6e6ae1cc3d fixed bugs in CMakeLists.txt and Makefile 2019-05-03 23:03:04 -06:00
tangxifan e5a18b7cca Add CMakeSupport, TODO: create CMAKE support for yosys 2019-05-03 19:04:02 -06:00