tangxifan
|
6c44f321e5
|
[script] fixed a bug
|
2022-08-22 18:24:26 -07:00 |
|
tangxifan
|
2bbf2f02c9
|
[script] now return status on each arch upgrade task
|
2022-08-22 18:23:00 -07:00 |
|
tangxifan
|
3c9c11d451
|
[script] working on formatting
|
2022-08-22 18:02:38 -07:00 |
|
tangxifan
|
55e765a206
|
[script] slight improve on formatting
|
2022-08-22 18:00:14 -07:00 |
|
tangxifan
|
4a7c3fce93
|
[script] debugging format
|
2022-08-22 17:04:30 -07:00 |
|
tangxifan
|
2f5ea0cabb
|
[script] functional arch file converter; need to clean up formatting issues
|
2022-08-22 16:40:49 -07:00 |
|
tangxifan
|
4efc506762
|
[script] now change to use minidom and debugging the child removal
|
2022-08-22 16:33:49 -07:00 |
|
tangxifan
|
880d7122bf
|
[script] complete code; start debugging on arch file converter
|
2022-08-22 12:29:49 -07:00 |
|
tangxifan
|
5134ea2233
|
[script] save progress
|
2022-08-22 11:00:46 -07:00 |
|
tangxifan
|
a61d6a2685
|
[script] developing arch converting script
|
2022-08-22 10:34:29 -07:00 |
|
tangxifan
|
9ea4a7c90f
|
[script] fixed a bug
|
2022-08-01 19:18:41 -07:00 |
|
tangxifan
|
55c7b75ab6
|
[script] even when power analysis mode is turned off, if users define a act file, still use it
|
2022-08-01 18:13:57 -07:00 |
root
|
0da44ad1fc
|
[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
|
2022-08-02 08:02:28 +08:00 |
Ganesh Gore
|
daae02a614
|
Minor documentation update
|
2022-05-08 13:03:16 -06:00 |
|
tangxifan
|
74045fc7a1
|
[Script] Fix a bug
|
2022-02-14 23:11:42 -08:00 |
|
tangxifan
|
2990eb7406
|
[Script] Fixed a bug in task run when removing previous runs
|
2022-02-14 22:54:16 -08:00 |
|
tangxifan
|
1d3c9ff192
|
[Script] Adapt python scripts to support include directory
|
2022-02-01 13:55:25 -08:00 |
|
tangxifan
|
dd40057992
|
[Script] Fixed a bug which causes errors when removing run-directory
|
2022-01-25 13:56:42 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
fb2e4377c8
|
Added missing changes from previous commit.
|
2022-01-17 19:42:40 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
Awais Abbas
|
fc52a4696c
|
Yosys only support added in OpenFPGA
|
2022-01-06 14:44:11 +05:00 |
nadeemyaseen-rs
|
1ea56b2d18
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-18 00:00:55 +05:00 |
|
Aram Kostanyan
|
a355977420
|
Adding Yosys+Verific support.
|
2021-10-29 18:34:27 +05:00 |
|
nadeemyaseen-rs
|
274252438a
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-10-20 20:13:46 +05:00 |
Christophe Alexandre
|
c42acec81e
|
Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
|
2021-10-18 10:45:35 +00:00 |
|
Christophe Alexandre
|
c3dd704bf3
|
Fixing typo in run_fpga_flow.py
|
2021-10-18 09:13:42 +00:00 |
|
Christophe Alexandre
|
d411967159
|
Fixing small typo in run_fpga_flow.py
|
2021-10-15 10:01:12 +00:00 |
|
tangxifan
|
6adf439081
|
Merge remote-tracking branch 'upstream/master'
|
2021-09-01 14:19:00 -07:00 |
Will
|
c31c1d8b04
|
Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
|
2021-08-13 11:08:09 -04:00 |
|
tangxifan
|
8baf60603a
|
[Script] Patching the run_fpga_task.py on pin constraint files
|
2021-07-02 15:59:29 -06:00 |
|
Ganesh Gore
|
c67807868c
|
[bugFix] Benchamrk variable declaration
|
2021-07-02 15:26:39 -06:00 |
|
Ganesh Gore
|
edd5be2cae
|
[CI] Added testcase for benchmark variable
|
2021-07-02 12:51:34 -06:00 |
|
Ganesh Gore
|
1de1f2f2e2
|
[FLOW] Variable in capital case
|
2021-07-01 22:26:00 -06:00 |
|
Ganesh Gore
|
81f9dff9ff
|
[Flow] Allows benchmark specific var declaraton
|
2021-07-01 22:19:53 -06:00 |
komaljaved-rs
|
6559f71082
|
added ci_scripts
|
2021-07-01 15:07:37 +05:00 |
|
tangxifan
|
7119075253
|
[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
|
2021-06-29 15:52:42 -06:00 |
|
tangxifan
|
fd580bb36f
|
[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
|
2021-06-22 11:45:23 -06:00 |
|
tangxifan
|
f9e66e1bae
|
[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
|
2021-06-21 15:27:12 -06:00 |
|
tangxifan
|
fce84e564d
|
[Script] Patch on missing string to show in error message
|
2021-06-18 11:20:35 -06:00 |
|
tangxifan
|
0e01177cf0
|
[Script] Now openfpga flow script output detailed error message when task is not found
|
2021-06-18 11:01:45 -06:00 |
|
tangxifan
|
781880ed93
|
[Script] Add tolerance options to check qor script
|
2021-03-23 12:26:33 -06:00 |
|
tangxifan
|
adfbd28a7a
|
[Script] Add a simple QoR checker
|
2021-03-23 11:06:16 -06:00 |
|
tangxifan
|
e1f8b252b1
|
Merge branch 'master' into yosys_heterogeneous_block_support
|
2021-03-16 20:05:21 -06:00 |
|
tangxifan
|
090f483a11
|
[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
|
2021-03-16 16:45:57 -06:00 |
|
tangxifan
|
b42541d84e
|
[Flow] Support multiple iterations in rewriting yosys scripts
|
2021-03-10 14:10:35 -07:00 |
|
tangxifan
|
035043d0d8
|
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
|
2021-03-10 13:36:11 -07:00 |
|
tangxifan
|
5d46537b5b
|
[Script] Allow users to specify custom post-synthesis verilog for simulation
|
2021-03-10 11:45:55 -07:00 |
|
tangxifan
|
aafd87c3f9
|
[Flow] Update flow-run to support custom yosys rewrite scripts
|
2021-03-10 11:36:29 -07:00 |