BaudouinChauviere
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a176bf3a19
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Update file_organization.rst
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2019-04-01 16:28:48 -06:00 |
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BaudouinChauviere
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01371ce54d
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Update customize_subckt.rst
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2019-04-01 16:27:06 -06:00 |
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BaudouinChauviere
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1ea7ec3265
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Update spice_simulation.rst
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2019-04-01 16:26:02 -06:00 |
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BaudouinChauviere
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cfdc072164
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Update file_organization.rst
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2019-04-01 16:25:09 -06:00 |
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BaudouinChauviere
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fcc3bf0967
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Update command_line_usage.rst
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2019-04-01 16:23:24 -06:00 |
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BaudouinChauviere
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f4b72bd4e1
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Update link_circuit_modules.rst
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2019-04-01 16:21:59 -06:00 |
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BaudouinChauviere
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ce300c196c
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Update circuit_modules.rst
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2019-04-01 16:13:23 -06:00 |
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BaudouinChauviere
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6e065ef3b3
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Update tech_lib.rst
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2019-04-01 16:09:31 -06:00 |
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BaudouinChauviere
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aed779ca3d
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Update spice_sim_setting.rst
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2019-04-01 16:08:00 -06:00 |
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BaudouinChauviere
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4900caaed9
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Update generality.rst
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2019-04-01 16:04:17 -06:00 |
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BaudouinChauviere
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33df25366c
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Update eda_flow.rst
Correction fix
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2019-04-01 16:02:47 -06:00 |
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BaudouinChauviere
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d6261f1f59
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Update motivation.rst
Typo and better explanations correction
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2019-04-01 15:57:04 -06:00 |
Baudouin Chauviere
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39f7b0b9a2
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Update of the doc for better fit with the current version
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2019-04-01 11:55:28 -06:00 |
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Baudouin Chauviere
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c4b42726c4
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fixes easing thehandling by the user.
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2019-03-31 07:55:05 -06:00 |
tangxifan
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b06df18a89
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Update rr_graph_area.c
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2019-03-11 21:46:42 +08:00 |
AurelienUoU
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213f94ddee
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Correct preconfiguration
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2019-01-31 16:43:47 -07:00 |
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tangxifan
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5e36aa82c5
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fixa bug in determining mux structure
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2019-01-22 13:54:50 -07:00 |
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Baudouin Chauviere
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32d1132bf8
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Addition of the dependencies in the documentation of the compilation
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2019-01-10 23:28:48 -07:00 |
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BaudouinChauviere
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3ca23f2026
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Update macos_compilation.md
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2019-01-10 22:04:10 -08:00 |
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BaudouinChauviere
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a904e4a37b
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Update red_hat_compilation.md
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2019-01-10 22:03:55 -08:00 |
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BaudouinChauviere
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568a5a0e92
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Update ubuntu_compilation.md
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2019-01-10 22:03:37 -08:00 |
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Baudouin Chauviere
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f3e7ae0823
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Hot fix
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2019-01-10 17:37:15 -07:00 |
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tangxifan
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b8187bbca5
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fix a bug for supporting default circuit_model of LUTs and FFs
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2019-01-10 15:10:05 -07:00 |
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Baudouin Chauviere
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9c8444da43
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update of the examples supplied to get the right paths
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2019-01-10 00:06:20 -07:00 |
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Baudouin Chauviere
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4ae3aa517c
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go.sh replaces the paths now
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2019-01-09 23:16:43 -07:00 |
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Baudouin Chauviere
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510c27f816
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Removed commercial scripts, replaced by academia ones
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2019-01-09 11:56:07 -07:00 |
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Baudouin Chauviere
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3b4fc16c60
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Adding help message on the go.sh
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2019-01-09 11:54:28 -07:00 |
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tangxifan
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66701838ff
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update relative path in ARCH XML
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2019-01-08 11:41:24 -07:00 |
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AurelienUoU
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b80e435548
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Correct manual testbench generation bug
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2019-01-07 18:03:56 -07:00 |
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BaudouinChauviere
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5dbcfa6d70
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Repair broken link
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2019-01-03 18:26:30 +01:00 |
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BaudouinChauviere
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28010f6c91
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Testing another link method
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2019-01-03 18:24:06 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
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30f2ada557
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Repaired broken links
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2019-01-03 18:18:03 +01:00 |
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tangxifan
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349e634fef
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Update README.md
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2018-12-30 14:37:17 -07:00 |
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tangxifan
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9f3da4d1a5
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Update README.md
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2018-12-30 14:35:07 -07:00 |
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LNIS-Projects
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77dd7f3e04
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correction of the name of the figure
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2018-12-29 01:45:45 +01:00 |
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LNIS-Projects
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0f6ac32f43
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Further resizing
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2018-12-29 01:44:24 +01:00 |
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LNIS-Projects
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38a3b01520
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Resize the images
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2018-12-29 01:42:43 +01:00 |
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Baudouin Chauviere
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9ee50de26a
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Adding information on the layout
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2018-12-29 01:14:26 +01:00 |
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Baudouin Chauviere
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0a5391c14f
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Addition of some illustrations
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2018-12-26 18:16:16 +01:00 |
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LNIS-Projects
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de7d646fa0
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Update func_verify.rst
Functional Verification documentation
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2018-12-26 18:05:24 +01:00 |
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LNIS-Projects
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c0626e9a1c
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Adding the Verification Step from ModelSim
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2018-12-26 18:00:03 +01:00 |
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AurelienUoU
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7ff245448b
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Add new benchmark and modify go.sh to use it
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2018-12-26 04:24:26 -07:00 |
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LNIS-Projects
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c506e16d33
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Update command_line_usage.rst
Small fix
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2018-12-22 14:46:15 +01:00 |
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LNIS-Projects
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ba303450e2
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Update file_organization.rst
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2018-12-22 14:45:00 +01:00 |
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LNIS-Projects
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5fa6c84087
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New fpga_verilog commands documented
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2018-12-22 14:39:51 +01:00 |
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LNIS-Projects
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41067f6ac1
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Update .travis.yml
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2018-12-14 16:13:05 -07:00 |
Robert Weischedel
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1b6d5b3b5d
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Update .travis.yml
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2018-12-14 15:30:25 -07:00 |
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AurelienUoU
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2fd05f269e
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
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2018-12-14 14:49:04 -07:00 |
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AurelienUoU
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21dc8a006f
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Change simulator script generation (waves)
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2018-12-14 14:40:04 -07:00 |
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LNIS-Projects
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c0e49b7d4d
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Update .travis.yml
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2018-12-14 14:16:04 -07:00 |