tangxifan
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7b4f06ed7d
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[test] validate mux2 at last stage
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2024-09-18 17:40:13 -07:00 |
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tangxifan
|
b215b868c1
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[HDL] Bug fix in HDL netlist due to port name mismatching
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2021-02-01 11:35:25 -07:00 |
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tangxifan
|
e0e2506e32
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[HDL] Remove redundant comments
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2021-02-01 10:33:08 -07:00 |
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tangxifan
|
39543f7945
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[HDL] Add carry mux2 to cell library
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2021-02-01 10:23:46 -07:00 |
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tangxifan
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5eb04e6fff
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[HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals
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2020-11-22 20:53:32 -07:00 |
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tangxifan
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019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |