10774dc15c
[Doc] Updated documentation about new syntax in fabric key
2021-09-21 17:01:52 -07:00
d9d959709c
[Doc] Add missing figures
2021-09-20 20:31:53 -07:00
3146d2484f
[Doc] Update documentation on the WLR definition for circuit model
2021-09-20 17:21:33 -07:00
73d21c9730
[Doc] Update doc about how to use the QuickLogic memory bank
2021-09-10 15:30:37 -07:00
801b91f776
Merge branch 'master' into tutorials
2021-08-31 17:17:40 -07:00
1c09b8c3e0
fixed python instruction
2021-08-17 10:18:51 -06:00
814d290463
Merge branch 'master' into tutorials
2021-08-05 10:24:34 -06:00
c867c7e628
Update index to include FAQ page
2021-07-28 10:14:31 -06:00
2bb76e4a82
Update to include suggested changes
2021-07-28 10:13:25 -06:00
17d3fb5d5e
Add FAQ to source folder to go along in appendix
2021-07-28 10:10:17 -06:00
a8a8c25a21
Update compile.rst
2021-07-26 15:18:23 -06:00
1c0bec1c5a
Update compile.rst
2021-07-26 15:17:25 -06:00
3ce866f2eb
Update compile.rst
2021-07-26 15:12:59 -06:00
43afaca17c
[Doc] Add more details about the new syntax
2021-07-01 23:51:54 -06:00
0851075bc9
[Doc] Update documentation about the new feature in pin constraint file
2021-07-01 23:47:36 -06:00
ac9046b7d2
[Doc] Remove ``define_simulation.v`` since it is no longer needed.
2021-06-29 15:38:35 -06:00
30027b8c15
[Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init'
2021-06-25 15:27:15 -06:00
11d0283771
[Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream'
2021-06-25 15:11:12 -06:00
507f5ee54c
[Doc] Update documentation about time unit support in writing simulation file
2021-06-25 10:34:43 -06:00
8e2ba718d0
[Doc] update documentation on the new option '--testbench_type'
2021-06-25 10:16:48 -06:00
779437cd37
[Doc] Update documentation to remove out-of-date options related to signal_init
2021-06-24 17:07:15 -06:00
de550ac550
Merge branch 'master' into tutorials
2021-06-16 14:00:31 -06:00
7787fe9795
update reference to match doc page
2021-06-16 12:46:43 -06:00
858bb2f21e
fix mistake in first line of page
2021-06-16 12:45:04 -06:00
624e9f3bb7
Update notation at top to match pages in doc
2021-06-16 12:44:01 -06:00
ece6e92f06
Add video at top of page
2021-06-16 12:29:17 -06:00
7a303463c3
Update shell_shortcuts.rst
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Update grammar. <_openfpga_task_args> no longer works
2021-06-14 15:34:13 -06:00
5e8b5d641f
Update compile.rst
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update grammar
2021-06-14 14:51:19 -06:00
1a2ced678e
Update tech_highlights.rst
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Update grammar and add link to standard_cell_library tutorial
2021-06-14 14:34:12 -06:00
d0549f10b3
Make a :ref: for tutorial
2021-06-14 14:28:21 -06:00
9585e1d3b5
[Doc] Update documentation about 'default_net_type' option in testbench generators
2021-06-14 14:00:34 -06:00
dc13325639
Update motivation.rst
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Fixing grammar and spacing
2021-06-14 13:44:20 -06:00
b719419931
[Doc] Update documentation on the FPGA-Verilog commands in openfpga shell; Deprecated the 'write_verilog_testbench' command
2021-06-09 16:59:02 -06:00
54a53bc988
[Doc] Update documentation on the minor changes on bitstream file for memory bank protocol
2021-06-07 17:58:00 -06:00
0fee741008
[Doc] Update documentation on the minor changes on fabric bitstream file format
2021-06-07 14:22:35 -06:00
c30be6e95e
[Doc] Update documentation about the fast configuration for write bitstream command
2021-06-04 20:00:28 -06:00
059e74b4ef
[Doc] Add --fast configuration option to documentation for 'write_full_testbench'
2021-06-04 15:17:00 -06:00
b83d8826fb
[Doc] Update documentation on the testbench organization/waveforms
2021-06-03 16:54:13 -06:00
9bcaa820ae
[Doc] Update documentation for the new command 'write_full_testbench'
2021-06-03 16:18:07 -06:00
16ae23f33e
[Doc] Update notes about compilation guidelines
2021-05-24 16:26:59 -06:00
9b40e74e25
[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples
2021-05-24 15:24:50 -06:00
21a18069a1
[Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples
2021-05-24 14:50:55 -06:00
b6b98a75b8
[Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model;
2021-05-24 13:03:40 -06:00
24f83f0058
[Doc] Update documentation about the new command 'report_bitstream_distribution'
2021-05-07 11:54:33 -06:00
1bae59dc6a
[Doc] Update documentation for the write_io_mapping command
2021-04-27 14:54:57 -06:00
d7426808ba
Merge pull request #299 from hitblunders/master
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Updated compile.rst
2021-04-26 00:26:07 -06:00
62dc5a3856
[Doc] Update documentation about the new syntax introduced for pin binding between operating modes and physical modes
2021-04-24 16:02:24 -06:00
cc92c27fde
Update compile.rst
2021-04-24 14:01:52 +05:30
2e1cc5499d
[Doc] Add disclaimer for limitations when using repack pin constraints
2021-04-21 14:14:54 -06:00
9b3dcc65bd
[Doc] Add new bitstream setting syntex 'interconnect' to documentation
2021-04-19 16:37:21 -06:00
986ea492f6
Fix grammar line 38: lookup table ->Look-Up Table
2021-04-19 14:16:40 -06:00
bc6e9746c2
Fix more grammar mistakes
2021-04-19 09:48:42 -06:00
8431337f39
Fix grammar errors in fig captions and elsewhere
2021-04-19 09:36:13 -06:00
86c856d35a
Fix reference links
2021-04-19 09:25:54 -06:00
cd6beb5789
Add one more link to fabric_netlists
2021-04-19 09:14:47 -06:00
f8810940c3
Update links
2021-04-19 09:10:17 -06:00
fcb7ee3283
Update to properly reference fabric netlist page
2021-04-19 09:05:30 -06:00
5010fb1e7f
Update hyperlinks
2021-04-19 08:52:05 -06:00
291638ee0f
Trying to resolve hyperlink to right location
2021-04-19 08:45:02 -06:00
beed1ce31e
replace hyperlink with more stable :ref: link
2021-04-19 08:38:09 -06:00
410c6a12ff
Update figures to be more accurate and clean
2021-04-16 11:46:12 -06:00
221822f0f0
update figures to correctly display out ports
2021-04-16 11:33:01 -06:00
423d814730
Update to include new figures
2021-04-13 16:04:20 -06:00
eff784e77b
Upload new figures for spypad tutorial
2021-04-13 15:53:51 -06:00
46f60d0704
Provide more explanation in Pre-Built Spypads
2021-04-12 18:10:36 -06:00
0606479bf8
Edit figures to better fit page
2021-04-12 17:53:31 -06:00
bb5cd1de47
Update to fix :numref: error example figure
2021-04-12 17:09:16 -06:00
a0b01dccc7
Update spypads_tutorial.rst to address comments
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Add links to github OpenFPGA architecture files, reference fig_gpout_ports, instead of emphasize lines switch to numbering the important lines
2021-04-12 17:02:56 -06:00
64e8e623a5
Update to fix links to proper syntax
2021-04-12 16:14:00 -06:00
bad49cdb75
Update to change Spypads to spypads
2021-04-12 16:07:38 -06:00
1744ce594e
Rename Spypads_tutorial.rst to spypads_tutorial.rst
2021-04-12 16:06:44 -06:00
90df365259
Fix a spacing issue on line 250
2021-04-12 14:21:53 -06:00
198882da89
Update link to From Verilog to Verification
2021-04-12 14:20:40 -06:00
b176ca6c0c
Update to improve readability
2021-04-12 14:13:41 -06:00
a2c2b634e6
Update link for _user_defined_template.v
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This ensures it goes to the correct page after pull request 274 no longer works
2021-04-12 14:00:54 -06:00
f626b17d04
Update user_defined_temp_tutorial
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Change "example" in the beginning of the page to "tutorial" for clarity
2021-04-12 13:58:19 -06:00
9b7001bc0f
Merge branch 'master' into tutorials
2021-04-10 17:16:09 -06:00
e5b47b7d3d
[Doc] Update documentation on the changes on fabric bitstream file formats
2021-04-10 15:45:39 -06:00
62da6b467d
Update tutorial to correctly display code
2021-04-09 16:15:44 -06:00
47dd6f8018
Update to include spypads tutorial
2021-04-09 16:04:37 -06:00
ce2e9c177b
Add figures for spypads tutorial
2021-04-09 16:03:41 -06:00
456a553884
Add Spypads tutorial
2021-04-09 16:02:37 -06:00
c6ae2a9b17
Fix opening paragraph
2021-04-09 09:15:25 -06:00
1d97cbf9b2
Update to improve readability
2021-04-09 08:38:20 -06:00
1534a3a7c7
Update Figure Citations
2021-04-02 16:02:41 -06:00
b4945a3c1e
Update to change information errors
2021-04-02 15:56:56 -06:00
d5ec17867d
Add files via upload
2021-04-02 14:49:58 -06:00
0655cda94d
Rescale PNG images downward
2021-04-02 14:45:47 -06:00
dc725dfd6f
Update to use cropped GTKWave PNGs
2021-04-02 14:43:37 -06:00
15fcf03e31
Crop GTKWaveforms
2021-04-02 14:42:23 -06:00
75891f800d
Update to fix reference link and shrink PNGs
2021-04-02 14:24:51 -06:00
71b96b9169
Update tutorial to swap in PNGs and fix errors
2021-04-02 14:22:03 -06:00
269776bb9c
Add Waveforms from GTKWave
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Upload a variety of different formats for the waveforms to find which one looks the best for the Cell Libraries tutorial page
2021-04-02 14:09:23 -06:00
dc991a912e
Update to fix grammar and spelling errors
2021-04-02 10:59:18 -06:00
b6feecc4c3
Update to fix SVG files to show data better
2021-04-02 10:47:36 -06:00
3c27027f76
Add files via upload
2021-04-02 10:46:51 -06:00
cfa2d7042d
Update Custom_Waveforms.svg
2021-04-02 10:44:36 -06:00
4c35df0df3
Update open_cell_libraries_tutorial.rst
2021-04-02 10:42:15 -06:00
baee023ba2
Update Control_Waveforms3.svg
2021-04-02 10:41:47 -06:00
65d2f82b94
Update Control_Waveforms3.svg
2021-04-02 10:41:29 -06:00
9849946fab
Update Control_Waveforms3.svg
2021-04-02 10:41:12 -06:00
821847f295
Update Control_Waveforms3.svg
2021-04-02 10:40:51 -06:00
96275f9c0e
Modify Control_Waveforms to fix height and width
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The height and width will now be set to the size of the viewbox
2021-04-02 10:39:20 -06:00
69b7c8f37a
Update to include new control_waveforms file
2021-04-02 10:32:31 -06:00
f03754561c
Add control_waveforms with smaller viewbox
2021-04-02 10:27:49 -06:00
c0256cdd87
Adjust height and width to see if image changes
2021-04-02 10:22:09 -06:00
d56ba1c5d7
Modify custom waveform to have a smaller viewbox
2021-04-02 10:13:51 -06:00
1bbf878498
Modify image to have a smaller viewbox
2021-04-02 10:13:13 -06:00
6393d11153
Update to highlight correct section of code
2021-04-02 10:04:53 -06:00
bff9e7aecd
Update hyperlinks to display properly
2021-04-02 10:02:26 -06:00
5f01e5e7a7
Update file
2021-04-02 09:54:54 -06:00
0072f4e51e
Merge branch 'master' into tutorials
2021-03-31 10:31:55 -06:00
c1036c6ac4
Match spelling to file name for cell_libraries
2021-03-31 10:04:51 -06:00
f8da09a80e
Update to include cell_library tutorial
2021-03-31 10:04:00 -06:00
36a6870cc0
Update tutorial to display waveforms
2021-03-30 21:59:18 -06:00
f963be4cae
Add files via upload
2021-03-30 21:56:43 -06:00
b8b024048e
Add first draft for Open Cell Libraries tutorial
2021-03-30 21:54:46 -06:00
eec52360ee
Merge branch 'master' into doc_patch
2021-03-23 21:33:05 -06:00
8ee86d78dd
Implement some of the final changes
2021-03-23 20:50:54 -06:00
16cefdba28
Fix minor changes in page
2021-03-23 18:19:14 -06:00
3dea033981
Implement more code blocks for cleaner page
2021-03-23 18:12:27 -06:00
ccfcae88d7
Update to remove clunky image with code-block
2021-03-23 17:41:55 -06:00
191ce358c7
Indent code-blocks
2021-03-23 17:29:34 -06:00
34a1df858b
Fix code-block syntax for XML
2021-03-23 17:25:32 -06:00
59ecaae23b
Update to use code-block syntax
2021-03-23 17:21:44 -06:00
07f05cc942
Update user_defined_temp_tutorial.rst
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Update to remove two images that were hard to read on the webpage and replace with code blocks
2021-03-23 17:16:27 -06:00
4317f7add7
Update file to display images w/caps
2021-03-23 16:50:52 -06:00
b194e9c395
Update index.rst
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Include link to user_defined_temp_tutorial file
2021-03-23 16:37:44 -06:00
4d0e06c332
Update user_defined_temp_tutorial
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Add more sections, robust instructions, and a link to documentation
2021-03-23 16:34:32 -06:00
a6dfba4500
Update to try and display tutorial images
2021-03-19 16:29:25 -06:00
e90bcdc4d5
Update to correctly include figure syntax
2021-03-19 16:21:45 -06:00
05ec5186a2
Update to see if .. image:: works for images
2021-03-19 16:18:21 -06:00
4e363660e7
Update to correct syntax for images
2021-03-19 16:14:51 -06:00
eea73ca2bf
Add user_defined_templates.rst file
2021-03-19 16:10:46 -06:00
7b23231909
Add images for user_defined_templates.v tutorial
2021-03-19 16:08:50 -06:00
19b2641839
Merge branch 'master' into doc_patch
2021-03-15 11:45:32 -06:00
fb7d76545e
[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
2021-03-15 11:40:09 -06:00
ff0faeb285
[Doc] Update documentation about the extended bitstream setting
2021-03-10 21:41:59 -07:00
c638e5bde5
[Doc] Update documentation for default net type option
2021-02-28 12:00:55 -07:00
01b9bf2a02
[Doc] Update num_region XML for config protocol
2021-02-18 21:58:30 -07:00
2eaec13351
[Doc] Reorganize tutorial documentation by grouping compilation guidelines, shell setup and tool guide into a section
2021-02-11 14:09:20 -07:00
702bd3bbd5
Merge pull request #231 from lnis-uofu/dev
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Extended LUT Support: Now accept external LUT netlists with embedded custom logic
2021-02-11 13:57:17 -07:00
184788880c
Merge pull request #224 from lnis-uofu/gg_docs
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[Docs] Added documentation for docker based run and shell shortcuts documentation
2021-02-11 09:26:29 -07:00
1c4dc9f74b
[Doc] Update documentation about the super LUT feature
2021-02-10 11:49:59 -07:00
c35cf72489
[Docs] Added OpenFPGA shortcut commands docs
2021-02-07 23:53:05 -07:00
cbd2064f59
[Docs] Updated docker based run documentation
2021-02-07 23:33:25 -07:00
9020577e80
Support SVG in Sphinx Latex building ( #220 )
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* [Doc] Try use image converter instead of svg2pdf which requires more dependencies
* [Doc] Add img converter to conf.py
* [Doc] Bug fix in importing imgconverter package
* [Doc] Try to fix the bug when importing python packages
* [Doc] bug fix
* [Doc] Try to use imgconverter rather than cairo
* [Doc] Add svg to latex config in sphinx configuration file
* [Doc] Try cairo svg converter
* [Doc] Correct bugs in compiling latexpdf
* [Doc] Use latest image in building readthedocs
* [Doc] Now use readthedocs docker image in building online documentation
* [Doc] Correct typo in readthedocs setting
* [Doc] Try to use inkscape converter as imgconverter converted SVG to black images
* [Doc] Try RSVG
2021-02-07 18:53:16 -07:00
b71966363b
[Doc] Try RSVG
2021-02-07 18:16:33 -07:00
3c1a538f7a
[Doc] Try to use inkscape converter as imgconverter converted SVG to black images
2021-02-07 17:53:58 -07:00
9c5368f912
[Doc] Correct bugs in compiling latexpdf
2021-02-07 16:17:54 -07:00
b556e6e7df
[Doc] Try cairo svg converter
2021-02-07 14:55:13 -07:00
40e9960618
[Doc] Add svg to latex config in sphinx configuration file
2021-02-07 12:40:14 -07:00
6492d8f3a8
[Doc] Try to use imgconverter rather than cairo
2021-02-07 12:27:45 -07:00
4551f13290
[Doc] bug fix
2021-02-07 12:06:23 -07:00
8f43ab6ca4
[Doc] Try to fix the bug when importing python packages
2021-02-07 12:00:48 -07:00
d96ffdc00c
[Doc] Bug fix in importing imgconverter package
2021-02-07 11:52:04 -07:00
49fc903bfb
[Doc] Add img converter to conf.py
2021-02-07 11:44:41 -07:00
6b6f4bc763
[Doc] Try use image converter instead of svg2pdf which requires more dependencies
2021-02-07 11:40:18 -07:00
05fea49b87
[Doc] Skip youtube video when building pdf; Apply SVG2PDF converter so that svg images can be included in the pdf
2021-02-07 10:35:20 -07:00
f6ec558bc2
[Doc] Now embed video in the documentation
2021-02-06 19:45:41 -07:00
a4b9199737
[Doc] Add tutorial about fabric netlist generation
2021-02-06 17:46:56 -07:00
1ff597ea66
[Doc] Add tutorial video links to documentation
2021-02-06 17:16:15 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
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Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
c4fe9a67f7
Merge pull request #215 from lnis-uofu/compilation_fixes
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Changed readthedocs.io dependencies link
2021-02-05 09:42:15 -07:00
9b5c64f35f
[Doc] Update documentation about disable_packing syntax
2021-02-04 16:41:24 -07:00
fe806f8ac3
changed docs dependencies link
2021-02-04 10:58:59 -08:00
d83158654c
[Doc] Add a draft documentation about the bitstream setting
2021-02-01 22:33:17 -07:00
0e16638dc2
[Doc] Update documentation about the changes on activity files
2021-01-29 11:49:07 -07:00
78ad9cd000
[Doc] Add version command/option to documentation
2021-01-27 16:06:45 -07:00
0a29529731
[Docs] Added CI/CD docs
2021-01-26 16:26:43 -07:00
d53d3963d4
[Doc] Broken link fix in config protocol documentation
2021-01-26 14:05:11 -07:00
97f8bccce3
[Doc] Add openfpga floorplanning to the overview part of documentation
2021-01-26 14:00:51 -07:00
4d5b63a685
[Doc] Fine-tune format on FPGA-SDC motivation
2021-01-26 11:04:31 -07:00
22a01cdb05
[Doc] Fine-tuned figure about openfpga tools to provide a clear borderline between openfpga shell and other tools/files
2021-01-26 10:36:34 -07:00
9fefe1502f
[Doc] Typo fix on write_fabric_key option
2021-01-25 15:18:16 -07:00
dd0680246a
[Doc] Typo fix on fabric key command
2021-01-25 14:12:40 -07:00
1ba7e0663f
Merge pull request #176 from lnis-uofu/dev
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Documentation Formatting
2021-01-24 21:11:49 -07:00
e18c533657
[Doc] Add new openfpga shell command to documentation
2021-01-24 14:48:56 -07:00
815468ac65
[Doc] Add shortcut to call pin constraint option to documentation
2021-01-20 09:20:51 -07:00
977ff52cb1
[Doc] Format openfpga command documentation by using option views
2021-01-19 20:26:38 -07:00
e9dc708d66
[Doc] Group file format documentation into a unified section
2021-01-19 19:44:44 -07:00
ac8c63553a
[Doc] Add file format index file
2021-01-19 18:07:53 -07:00
fbb5c0cf8f
[Doc] Add pin constraints to documentation
2021-01-19 18:04:45 -07:00
c7f02601ab
[Doc] Add repack design constraints to documentation
2021-01-17 12:59:46 -07:00
c4d3e7c50c
[Doc] Update documentation for the new XML syntax in simulation settings
2021-01-15 12:30:26 -07:00
0c808bec41
[Doc] Add clarification for defining multi-bit global tile ports
2021-01-09 20:00:16 -07:00
2324edc522
[Doc] Update documentation for upgraded tile annotation
2021-01-09 18:55:16 -07:00
226f6b8d6d
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
2021-01-04 18:30:04 -07:00
0e7c04878c
Merge remote-tracking branch 'origin/master' into replace_yosys
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Merging latest changes from master.
2020-12-14 20:57:26 -08:00
024bc17b84
[Doc] Bug fix on the incompatible sphinx bibtex version. Constrain to the right version.
2020-12-14 09:37:45 -07:00
3ccd6b80dd
Updating compile.rst file with updated compilation steps
2020-12-13 21:04:10 -08:00
406edeec89
[Doc] Typo fix
2020-12-04 15:07:02 -07:00
4fe190fa7e
[Doc] Bug fix in LUT circuit model documentation
2020-12-04 14:44:27 -07:00
8350b0f911
[Doc] Update documentation about default value definition in tile annotation
2020-12-02 17:08:34 -07:00
cc0114459a
[Doc] Enrich examples for LUT circuit models
2020-11-26 13:03:12 -07:00
62e804215b
[Doc] Add svg figures for LUT examples
2020-11-26 12:35:39 -07:00
b857135f4e
[Doc] Add clarification about which cells are applicable for signal initialization
2020-11-23 15:19:15 -07:00
2b9a97729e
[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
2020-11-23 15:09:47 -07:00
fd0e6814ea
[Doc] Update documentation about the pre-processing flags
2020-11-22 20:33:15 -07:00
f6126d1ed6
[Doc] Add illustrative example to diff between global ports definitions
2020-11-12 09:24:39 -07:00
bc43c876b0
[Doc] Update documentation for the rules in global port definition for tile ports
2020-11-11 14:10:11 -07:00
2c269c532a
[Doc] Update doc for the global port definition using physical tile port
2020-11-10 20:48:28 -07:00
056b7c0c79
[Doc] Update documentation about CCFF circuit model examples
2020-11-06 12:22:22 -07:00
55b14fa6b4
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into dev
2020-11-06 10:11:38 -07:00
849ecc7fc0
[Doc] Add notes for using the is_data_io syntax
2020-11-05 09:30:19 -07:00
9bce2f3818
[Doc] Update documentation for new XML syntax "is_data_io"
2020-11-05 09:28:46 -07:00
032cbfb8b2
Merge pull request #113 from LNIS-Projects/dev
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Multi-region support on Frame-based Configuration Protocol
2020-10-31 10:37:38 -06:00
be7f7592ae
[Doc] Update documentation about don't care bit in frame address
2020-10-30 22:13:28 -06:00
7e940980e1
[Doc] Update documentation about configuration regions for frame-based protocol
2020-10-30 21:52:01 -06:00
cd0d3dd798
Merge pull request #112 from LNIS-Projects/dev
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Multi-region Memory Bank Configuration Protocol Support
2020-10-29 18:39:44 -06:00
c2c384e24b
[Doc] update documentation about memory bank definition
2020-10-29 17:04:25 -06:00
ff9c17cba8
Merge pull request #111 from LNIS-Projects/dev
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Bug fix in tutorial due to renamed regression tests
2020-10-28 09:40:28 -06:00
efb0162e3f
[Doc] Bug fix in tutorial due to renamed regression tests
2020-10-28 08:58:19 -06:00
16128f0905
Merge pull request #107 from LNIS-Projects/dev
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Enable Customized Fabric Netlist Location in Verilog Testbench Generation
2020-10-12 13:47:40 -06:00
3aeea724de
[Documentation] Update for new options in fpga-verilog
2020-10-12 12:36:24 -06:00
5efe1ae77d
Merge pull request #106 from LNIS-Projects/dev
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Documentation update
2020-10-10 23:16:37 -06:00
ccaa697e5a
[Documentation] Add links to technical features to examples
2020-10-10 22:40:37 -06:00
00295a003f
Docs: Updated note to enable VPR's GUI
2020-10-06 20:47:43 -04:00
800931c840
[Documentation] Add configuration protocol to technical highlights
2020-10-06 12:16:15 -06:00
56ab63d939
[Documentation] Fix format in table
2020-10-06 12:02:15 -06:00
c8339fc473
[Documentation] Typo fix
2020-10-06 12:00:30 -06:00
113708c68f
[Documentation] Reorganization the overview part by adding technical highlights
2020-10-06 11:56:10 -06:00
02e21d115b
[Documentation] Update 3-rd party tool version requirements
2020-10-06 10:00:12 -06:00
67300af987
[Documentation] Update motivation with new set of figures
2020-09-29 16:52:16 -06:00
6817c045c2
[Documentation] Update tutorial about tooling
2020-09-29 16:24:52 -06:00
639d57016b
[Documentation] Update documentation about the multi-region configuration
2020-09-29 15:55:42 -06:00
462886fb5f
[Documentation] Update documentation for the multiple region support on configuration chain
2020-09-29 14:02:03 -06:00
94a1324f05
[Documentation] Remove deprecated XML syntax
2020-09-26 14:31:57 -06:00
f57fd273af
[Documentation] Update documentation for smart fast configuration
2020-09-23 21:28:06 -06:00
3d234d840b
[Documentation] Update documentation for the edge triggered attribute
2020-09-23 20:31:11 -06:00
7a2502ddf9
[documentation] add more guidelines about the vpr-openfpga architecture annotation
2020-09-02 22:47:14 -06:00
b5251ce5af
[documentation] update motivation figure and layout licenses
2020-09-01 11:07:50 -06:00
ac8e937a50
[Documentation] Update for default circuit model rules
2020-08-23 14:08:38 -06:00
fb5a5a2448
[documentation] remove the limitation on through channels
2020-08-19 20:12:49 -06:00
47f15729ad
update doc about the limitation on using tileable routing
2020-08-19 18:37:28 -06:00
d6d17675e2
update docoumentation about the constraints when using tileable rr_graph generator
2020-08-19 18:01:32 -06:00
161d660837
update documentation for the initial offset when mapping physical pins
2020-08-19 15:00:46 -06:00
53f87f44b4
update documentation for the multi-port support in physical pb_pin
2020-08-18 12:44:38 -06:00
cfd035bf8f
update tutorials about the verilog-to-verification
2020-08-17 14:33:51 -06:00
f773491f87
update documentation to sync with the new fabric bitstream format
2020-07-27 16:37:10 -06:00
50ac78f906
update documentation for the split fabric bitstream
2020-07-27 14:26:02 -06:00
fcd8a3cf4d
update doc format
2020-07-27 13:59:36 -06:00
a24754611c
update documentation about the 'width' syntax of fabric dependent bitstream
2020-07-27 13:56:57 -06:00
aef1d7ba63
bug fix in doc about showing example fabric bitstream
2020-07-26 22:50:06 -06:00
872a35fc60
update doc to fix format problem; add frame_view to doc
2020-07-26 22:39:33 -06:00
1f39540672
update documentation about fabric bitstream file formats
2020-07-26 21:38:33 -06:00
c3fd817bae
update documentation about new XML syntax max width
2020-07-24 16:33:01 -06:00
c26c268dcd
update documentation on fast configuration support for configuration chain
2020-07-15 13:55:32 -06:00
862d71f57a
remove obselete vpr7 XML syntax from documentation
2020-07-15 11:13:47 -06:00
cb0df2c1c6
update doc about technology binding between circuit library and device library
2020-07-15 11:05:33 -06:00
tangxifan
ANDREW HARRIS POND
bbleaptrot
Andrew Pond
ganeshgore
Parnabrita Mondal
Ganesh Gore
AurelienAlacchi
Andrew Pond
Lalit Sharma
Laboratory for Nano Integrated Systems (LNIS)
Andrew Lukefahr