tangxifan
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0f0d06aad7
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add non-LUT intermediate buffer to test and apply minor bug fix
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2019-09-18 15:04:51 -06:00 |
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tangxifan
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d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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tangxifan
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5abbfd6a0f
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add tileable routing to regression test
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2019-09-16 20:45:02 -06:00 |
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tangxifan
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f04565386f
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refactored behavioral mux branch verilog generation
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2019-08-27 18:39:25 -06:00 |
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tangxifan
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de8a6bc833
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update regression tests
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2019-08-26 21:00:15 -06:00 |
Ganesh Gore
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7a3ff94116
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Added blif task in travis script
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2019-08-25 01:28:21 -06:00 |
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Ganesh Gore
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937ebd1b85
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-08-25 00:53:18 -06:00 |
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Ganesh Gore
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f558437ae1
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Added task for vpr_blif flow
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2019-08-25 00:23:39 -06:00 |
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Ganesh Gore
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89589ddc1c
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-08-22 18:46:51 -06:00 |
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Ganesh Gore
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2f0acfad23
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Updated travis to run regression task
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2019-08-21 11:09:53 -06:00 |
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tangxifan
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59f1ac7310
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add missing files and try to refactor submodule essential
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2019-08-20 20:49:26 -06:00 |
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tangxifan
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5f55fc7b49
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add missing files and developing essential gates
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2019-08-20 20:43:46 -06:00 |
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tangxifan
|
60e8d2b29f
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add missing files and try to refactor submodule essential
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2019-08-20 16:13:08 -06:00 |
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Ganesh Gore
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8d0153d34e
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Added gitignore to skip run directory tracking
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2019-08-19 19:06:01 -06:00 |
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Ganesh Gore
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901932a4fc
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First draft: Working openfpga task flow
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2019-08-16 09:44:50 -06:00 |
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Ganesh Gore
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b82369dd96
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Added first draft of fpga_task script
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2019-08-09 00:17:06 -06:00 |