Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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59a622a910
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[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
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2021-10-30 14:34:37 -07:00 |
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tangxifan
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94328351be
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[Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts
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2021-10-30 12:00:06 -07:00 |
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tangxifan
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6b0409da60
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[Script] Add a template yosys script support only DSP mapping
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2021-03-23 15:32:10 -06:00 |