Commit Graph

1114 Commits

Author SHA1 Message Date
tangxifan ddfb0c4afd [core] now mock fpga top supports fpga core wrapper 2023-06-26 15:06:11 -07:00
tangxifan 83fa6a421e [core] code format 2023-06-26 10:06:17 -07:00
tangxifan 70f40cd21a [core] fixing bugs in the preconfig module when supporting dut module of fpga_core 2023-06-26 10:03:19 -07:00
tangxifan 919d6d8608 [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
tangxifan 205881d0e7 [core] fixed the bug when using fpga_core instead of fpga_top 2023-06-25 18:03:15 -07:00
tangxifan 150653287d [core] supporting io naming for verilog testbench generators 2023-06-25 15:29:27 -07:00
tangxifan 987a562e0f [core] fixed the bug when checking mapping status of fpga core ports 2023-06-23 17:21:52 -07:00
tangxifan 463332c77a [core] code complete for adding nets between top and core module 2023-06-23 13:21:25 -07:00
tangxifan b30148f8fb [core] apply more sanity checks on top module port 2023-06-23 12:37:46 -07:00
tangxifan 2484150ab6 [core] working on port addition to top module 2023-06-23 12:21:47 -07:00
tangxifan 8bd9ae02fd [core] io name map now supports dummy port direction 2023-06-23 11:09:33 -07:00
tangxifan 7961223eac [core] enabling io naming rules in fabric builder 2023-06-22 22:18:09 -07:00
tangxifan 61544af2b4 [core] start adding new options 2023-06-21 14:01:00 -07:00
tangxifan b2d1d1b6bd [core] fixed a bug on fpga bitstream when supporting fpga_core 2023-06-19 14:40:38 -07:00
tangxifan 299b42873d [core] fix no warning build 2023-06-19 13:01:43 -07:00
tangxifan a4f26798b0 [core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc 2023-06-19 11:59:48 -07:00
tangxifan 63ee0c980e [core] fixed some bugs 2023-06-18 22:12:54 -07:00
tangxifan d9499f2b40 [core] now fpga bitstream supports the wrapper module 2023-06-18 21:58:36 -07:00
tangxifan bdda695cc0 [core] format 2023-06-18 21:18:35 -07:00
tangxifan cef573529d [core] now fpga verilog can output fpga core netlist 2023-06-18 21:17:50 -07:00
tangxifan c7ade72200 [core] code complete for the core wrapper creator. Start debugging 2023-06-18 19:17:42 -07:00
tangxifan 8bc70b590a [core] developing fpga_core insertion 2023-06-17 23:42:45 -07:00
tangxifan ee59bdb675 [core] code format 2023-06-07 18:55:34 -07:00
tangxifan 327f7f4dab [core] now adapt to latest API of DeviceGrid 2023-06-07 18:54:48 -07:00
tangxifan b6c90eb99a [core] fixed several bugs which causes bgf and pcf support in mock wrapper failed 2023-05-27 12:13:16 -07:00
tangxifan e1feebc96d [core] fixing bugs on pcf and bgf support for mock efpga wrapper 2023-05-26 21:54:08 -07:00
tangxifan 0abc5af1a9 [core] fixed the bug supporting global nets 2023-05-26 20:44:04 -07:00
tangxifan a9e5e1af89 [core] now fabric netlist include mock wrapper 2023-05-26 18:49:57 -07:00
tangxifan 788b1495dd [core] split a big function to 4 sub functions so that we can efficiently reuse for mock wrapper 2023-05-26 17:31:07 -07:00
tangxifan f7afbfa0bd [core] fixed some bugs 2023-05-26 12:26:30 -07:00
tangxifan e9848c5728 [core] typo 2023-05-26 10:24:21 -07:00
tangxifan 45e25e4152 [core] hooking up API with command 2023-05-25 19:50:39 -07:00
tangxifan affe5c5d1e [core] developing mock wrapper generator 2023-05-25 18:50:47 -07:00
tangxifan ab263aa5b1 [core] code format 2023-05-25 15:02:03 -07:00
tangxifan 8d7429fc2b [core] adding the new command 'write_mock_fpga_wrapper' 2023-05-25 12:58:12 -07:00
tangxifan dab89322b3 [core] fixed the bug in I/O location map build-up when supporting subtiles 2023-05-04 09:51:05 +08:00
tangxifan cb0e6b9e17 [core] fixed a critical bug 2023-05-03 21:46:35 +08:00
tangxifan 6c48c57421 [core] fixed some bugs in the subtile support 2023-05-03 21:23:52 +08:00
tangxifan 7bedc965ac [core] supporting subtile 2023-05-03 17:30:58 +08:00
tangxifan 18b078d1d5 [core] fixed bugs which cause ci failed 2023-04-24 21:20:07 +08:00
tangxifan e11e4dc3f4 [core] comment on current limitations 2023-04-24 14:59:43 +08:00
tangxifan d9af8dd722 [core] did some dirty fix but now dv should pass. Not sure why usig a shorter bitstream does not work 2023-04-24 14:50:42 +08:00
tangxifan 679c6e9b43 [core] debugging 2023-04-24 14:05:51 +08:00
tangxifan 3c6a4d34d8 [core] code format 2023-04-24 13:36:59 +08:00
tangxifan 715765d81b [core] code complete for top testbench generator on ccffv2 upgrades 2023-04-24 13:34:44 +08:00
tangxifan 667d9df028 [core] developing testbench generator for ccff v2 2023-04-24 11:36:21 +08:00
tangxifan 1ba3c56cf3 [core] code format 2023-04-23 16:49:19 +08:00
tangxifan ba90f5020b [core] fixed some bugs which cause netlist generation failed 2023-04-23 16:48:14 +08:00
tangxifan 28b7a12f68 [core] code format 2023-04-23 14:31:35 +08:00
tangxifan bd511ba515 [core] fixed syntax errors 2023-04-23 14:26:08 +08:00