Commit Graph

2780 Commits

Author SHA1 Message Date
tangxifan 1e47203c7c [Tool] Auto-generated gate Verilog netlist should not contain any signal initalization 2020-11-02 18:35:26 -07:00
tangxifan e4d974c5c8 [Tool] Split io location mapping builder from fabric builder 2020-11-02 18:27:34 -07:00
tangxifan 1fd899ecee [Tool] Relex logic block checking codes to skip zero-capacity nodes 2020-11-02 16:57:19 -07:00
tangxifan 3b49e6d090 [Arch] Patch embedded IO architecture by forcing only 1 pad per block 2020-11-02 15:39:31 -07:00
tangxifan c512644a09 [Arch] Patch embedded I/O example architecture 2020-11-02 15:16:19 -07:00
tangxifan 7e9e0ec9d4 [HDL] Bug fix in I/O HDL code 2020-11-02 15:15:45 -07:00
tangxifan f1ce816d6c [Tool] Force inout port to be mandatory for I/O cells 2020-11-02 15:14:02 -07:00
tangxifan 2f237a6240 [HDL] Add HDL codes for embedded I/Os 2020-11-02 14:01:27 -07:00
tangxifan 55b77ac6cb [Arch] Bug fixed in embedded FPGA architecture 2020-11-02 13:57:15 -07:00
tangxifan e850dd5314 [Tool] Relax checking codes for embedded I/O circuit models 2020-11-02 13:54:31 -07:00
tangxifan a7e7fa2005 [Arch] Update arch with true embedded I/O definition 2020-11-02 13:29:40 -07:00
tangxifan 65ca53ac98 [Test] Update test case with the new arch name 2020-11-02 13:16:42 -07:00
tangxifan 8c8190047f [Arch] Rename architecture files for embedded I/Os 2020-11-02 13:15:19 -07:00
tangxifan a346c529aa [Test] Deploy test case to CI 2020-11-02 12:29:20 -07:00
tangxifan bc00dee858 [Test] Add test case for embedded I/O 2020-11-02 12:28:25 -07:00
tangxifan f86f43d287 [Arch] Add openfpga architecture file for constrained pin equivalence 2020-11-02 12:27:40 -07:00
tangxifan 795b30f76b [Arch] Add VPR architecture with partial pin equivalence 2020-11-02 11:54:25 -07:00
tangxifan 032cbfb8b2
Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
2020-10-31 10:37:38 -06:00
tangxifan be7f7592ae [Doc] Update documentation about don't care bit in frame address 2020-10-30 22:13:28 -06:00
tangxifan 6b25cf720d [Tool] Comment on the memory efficiency on fabric bitstream address storage 2020-10-30 22:09:48 -06:00
tangxifan 7e940980e1 [Doc] Update documentation about configuration regions for frame-based protocol 2020-10-30 21:52:01 -06:00
tangxifan 940eb937f2 [Test] add multi-region configuration frame test cases to CI 2020-10-30 21:21:11 -06:00
tangxifan b78f8bec16 [Tool] Bug fixed for multi-region configuration frame 2020-10-30 21:19:20 -06:00
tangxifan 5bcd559851 [Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification 2020-10-30 17:29:04 -06:00
tangxifan 4c14428400 [Test] Add test case for fast configuration support on multi-region frame-based configuration protocol 2020-10-30 10:50:00 -06:00
tangxifan ca7d43275d [Test] Add test case for multi_region configuration frame 2020-10-30 10:48:29 -06:00
tangxifan 29da368742 [Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories 2020-10-30 10:46:47 -06:00
tangxifan b701bd2640 [Arch] Add multi-region architecture example for frame-based protocol 2020-10-30 10:45:14 -06:00
tangxifan 0d77916041 [Tool] Support multi-region frame-based configuration protocol 2020-10-30 10:43:11 -06:00
Laboratory for Nano Integrated Systems (LNIS) cd0d3dd798
Merge pull request #112 from LNIS-Projects/dev
Multi-region Memory Bank Configuration Protocol Support
2020-10-29 18:39:44 -06:00
tangxifan 1d930d1b5d [Architecture] Add missing arch files and bug fix 2020-10-29 18:08:26 -06:00
tangxifan 8ef6ae32fb [Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol 2020-10-29 17:35:55 -06:00
tangxifan c2c384e24b [Doc] update documentation about memory bank definition 2020-10-29 17:04:25 -06:00
tangxifan 1ad591c08c [Test] Add smart fast configuration test cases for multi-region memory banks to CI 2020-10-29 16:33:54 -06:00
tangxifan 153b265a6d [Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set 2020-10-29 16:32:05 -06:00
tangxifan 241ebf054a [Test] Add a test case for validating fast configuration techniques on multi-region memory banks 2020-10-29 16:29:46 -06:00
tangxifan 51f2e7f625 [Test] Add multi-region memory bank test case to CI 2020-10-29 16:28:03 -06:00
tangxifan 987eccf586 [Tool] Bug fix in multi-region memory bank; Basic test passed 2020-10-29 16:26:45 -06:00
tangxifan ff386001c4 [Test] Add openfpga task for multi-region memory banks 2020-10-29 13:56:32 -06:00
tangxifan 7534474423 [Arch] Add architecture for multiple-region memory banks 2020-10-29 13:54:51 -06:00
tangxifan 448e88645a [Tool] Support multiple memory banks in top-level module 2020-10-29 12:42:03 -06:00
tangxifan bd49ea95d4 [Tool] Add function to comput configuration bits by region 2020-10-28 12:37:09 -06:00
tangxifan 446f982410 [Tool] Add warning when number of regions defined in fabric key is different than architecture 2020-10-28 11:43:05 -06:00
Laboratory for Nano Integrated Systems (LNIS) ff9c17cba8
Merge pull request #111 from LNIS-Projects/dev
Bug fix in tutorial due to renamed regression tests
2020-10-28 09:40:28 -06:00
tangxifan efb0162e3f [Doc] Bug fix in tutorial due to renamed regression tests 2020-10-28 08:58:19 -06:00
Laboratory for Nano Integrated Systems (LNIS) 8b85f22533
Merge pull request #109 from LNIS-Projects/dev
Frontpage README Update with more links to documentation pages
2020-10-27 21:52:35 -06:00
tangxifan 29431394a8 [Doc] Add links to the technical summary in documentation for README 2020-10-27 10:08:25 -06:00
tangxifan 90e6021e43 [Doc] Update README with more links to documentation 2020-10-27 09:53:57 -06:00
Laboratory for Nano Integrated Systems (LNIS) d984547258
Merge pull request #108 from LNIS-Projects/dev
Add test cases for constant inputs of routing multiplexers
2020-10-14 22:33:14 -06:00
tangxifan 63f130d948 [Test] Deploy none constant input test case to CI 2020-10-13 12:04:07 -06:00