tangxifan
|
6b92299e39
|
[core] start working on the net build-up for tile instances under the top-level module
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2023-07-20 17:38:13 -07:00 |
|
tangxifan
|
88c5d122ca
|
[core] syntax
|
2023-07-20 17:12:10 -07:00 |
|
tangxifan
|
db179ec4bb
|
[core] split tile instance builder and the classic fine-grained builder
|
2023-07-20 17:07:07 -07:00 |
|
tangxifan
|
ef214f4590
|
[core] code format
|
2023-07-20 17:00:29 -07:00 |
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tangxifan
|
6458580e3e
|
[core] move child instance builder to a separated source file as these codes are expanding in size
|
2023-07-20 16:59:39 -07:00 |
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tangxifan
|
bd265334b5
|
[core] added tile instances to top module builder
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2023-07-19 23:26:55 -07:00 |
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tangxifan
|
a06b9a0f48
|
[core] now start to develop the tile instances under the top module
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2023-07-19 22:22:07 -07:00 |
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tangxifan
|
2e69eebea0
|
[core] now tile module builder is working
|
2023-07-19 17:23:44 -07:00 |
|
tangxifan
|
0d03d7b483
|
[core] now fabric tile cache both grid and gsb coord for pb
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2023-07-19 17:20:53 -07:00 |
|
tangxifan
|
778d03610c
|
[core] debugging
|
2023-07-19 15:27:05 -07:00 |
|
tangxifan
|
001b3b3f8b
|
[core] debugging
|
2023-07-19 14:38:07 -07:00 |
|
tangxifan
|
d03fa92ddf
|
[core] debugging
|
2023-07-19 12:49:35 -07:00 |
|
tangxifan
|
48e207d3e4
|
[core] debugging
|
2023-07-19 12:22:57 -07:00 |
|
tangxifan
|
6607bb7e48
|
[core] now fpga verilog supports tile modules
|
2023-07-18 22:35:22 -07:00 |
|
tangxifan
|
5ae146bd86
|
[core] finish up tile module builder
|
2023-07-18 21:17:40 -07:00 |
|
tangxifan
|
0dcec9d8e5
|
[core] finishing up tile module builder
|
2023-07-18 17:56:27 -07:00 |
|
tangxifan
|
403ed4ea60
|
[core] still developing tile module port and net builder
|
2023-07-18 16:03:47 -07:00 |
|
tangxifan
|
aabcc25567
|
[core] developing tile module port and net builder
|
2023-07-17 23:06:55 -07:00 |
|
tangxifan
|
ba4b7e3522
|
[core] developing tile module builder
|
2023-07-16 15:18:09 -07:00 |
|
tangxifan
|
98c598cec2
|
[core] unique tile identifier done
|
2023-07-15 22:54:33 -07:00 |
|
tangxifan
|
ea8d128789
|
[core] syntax
|
2023-07-15 20:29:21 -07:00 |
|
tangxifan
|
c2ef5ca408
|
[core] developing top-left style tile info
|
2023-07-14 22:48:44 -07:00 |
|
tangxifan
|
091ac88c7e
|
[lib] code format
|
2023-07-14 12:16:40 -07:00 |
|
tangxifan
|
3bc959dcec
|
[lib] create tile config lib and start integration to core
|
2023-07-14 12:13:31 -07:00 |
|
tangxifan
|
c58035dbd4
|
[core] start developing option --group_tile for build_fabric
|
2023-07-14 11:01:04 -07:00 |
|
tangxifan
|
3de4d3fc09
|
[core] add a new command 'write_fabric_key' and now writer supports module-level keys
|
2023-07-08 18:12:51 -07:00 |
|
tangxifan
|
433391eec4
|
[core] move new functions to a separated source file
|
2023-07-07 15:03:03 -07:00 |
|
tangxifan
|
d3aa4c53d0
|
[core] now support rebuild configuarable children for ccff submodules
|
2023-07-07 14:51:21 -07:00 |
|
tangxifan
|
a1b13b8e12
|
[core] overload submodule configurable children from fabric key
|
2023-07-06 22:47:57 -07:00 |
|
tangxifan
|
d3109ee88b
|
[core] developing configurable children reloading from fabric key
|
2023-07-06 21:53:22 -07:00 |
|
tangxifan
|
ddfb0c4afd
|
[core] now mock fpga top supports fpga core wrapper
|
2023-06-26 15:06:11 -07:00 |
|
tangxifan
|
83fa6a421e
|
[core] code format
|
2023-06-26 10:06:17 -07:00 |
|
tangxifan
|
70f40cd21a
|
[core] fixing bugs in the preconfig module when supporting dut module of fpga_core
|
2023-06-26 10:03:19 -07:00 |
|
tangxifan
|
919d6d8608
|
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
|
2023-06-25 22:49:51 -07:00 |
|
tangxifan
|
205881d0e7
|
[core] fixed the bug when using fpga_core instead of fpga_top
|
2023-06-25 18:03:15 -07:00 |
|
tangxifan
|
150653287d
|
[core] supporting io naming for verilog testbench generators
|
2023-06-25 15:29:27 -07:00 |
|
tangxifan
|
987a562e0f
|
[core] fixed the bug when checking mapping status of fpga core ports
|
2023-06-23 17:21:52 -07:00 |
|
tangxifan
|
463332c77a
|
[core] code complete for adding nets between top and core module
|
2023-06-23 13:21:25 -07:00 |
|
tangxifan
|
b30148f8fb
|
[core] apply more sanity checks on top module port
|
2023-06-23 12:37:46 -07:00 |
|
tangxifan
|
2484150ab6
|
[core] working on port addition to top module
|
2023-06-23 12:21:47 -07:00 |
|
tangxifan
|
8bd9ae02fd
|
[core] io name map now supports dummy port direction
|
2023-06-23 11:09:33 -07:00 |
|
tangxifan
|
7961223eac
|
[core] enabling io naming rules in fabric builder
|
2023-06-22 22:18:09 -07:00 |
|
tangxifan
|
61544af2b4
|
[core] start adding new options
|
2023-06-21 14:01:00 -07:00 |
|
tangxifan
|
b2d1d1b6bd
|
[core] fixed a bug on fpga bitstream when supporting fpga_core
|
2023-06-19 14:40:38 -07:00 |
|
tangxifan
|
299b42873d
|
[core] fix no warning build
|
2023-06-19 13:01:43 -07:00 |
|
tangxifan
|
a4f26798b0
|
[core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc
|
2023-06-19 11:59:48 -07:00 |
|
tangxifan
|
63ee0c980e
|
[core] fixed some bugs
|
2023-06-18 22:12:54 -07:00 |
|
tangxifan
|
d9499f2b40
|
[core] now fpga bitstream supports the wrapper module
|
2023-06-18 21:58:36 -07:00 |
|
tangxifan
|
bdda695cc0
|
[core] format
|
2023-06-18 21:18:35 -07:00 |
|
tangxifan
|
cef573529d
|
[core] now fpga verilog can output fpga core netlist
|
2023-06-18 21:17:50 -07:00 |