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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 433fc73460 refactored local encoder support for Verilog MUX generation 2019-09-27 23:10:43 -06:00
tangxifan dbe1625267 Refactored Verilog wiring for formal verification ports in Switch Blocks 2019-09-27 13:51:22 -06:00