tangxifan
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c46c0fc97d
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bug fixing for SDC generator
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2019-04-26 14:07:44 -06:00 |
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tangxifan
|
46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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tangxifan
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b06df18a89
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Update rr_graph_area.c
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2019-03-11 21:46:42 +08:00 |
AurelienUoU
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213f94ddee
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Correct preconfiguration
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2019-01-31 16:43:47 -07:00 |
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tangxifan
|
5e36aa82c5
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fixa bug in determining mux structure
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2019-01-22 13:54:50 -07:00 |
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tangxifan
|
b8187bbca5
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fix a bug for supporting default circuit_model of LUTs and FFs
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2019-01-10 15:10:05 -07:00 |
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AurelienUoU
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b80e435548
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Correct manual testbench generation bug
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2019-01-07 18:03:56 -07:00 |
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AurelienUoU
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21dc8a006f
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Change simulator script generation (waves)
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2018-12-14 14:40:04 -07:00 |
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tangxifan
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ee6b1d6cd6
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adapt arch xml and act for demo
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2018-12-13 22:46:40 -07:00 |
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AurelienUoU
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cc5a01d476
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Fix waveform generation + add benchmark and update go.sh
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2018-12-11 22:21:39 -07:00 |
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AurelienUoU
|
f5ea3ff233
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Add an autochecked configuration free testbench
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2018-12-11 14:44:13 -07:00 |
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tangxifan
|
72fbd8d6a8
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update blif reader to identify clock signals
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2018-12-10 13:28:44 -07:00 |
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AurelienUoU
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a69c2e1882
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Add security in checking to avoid simulation glitch error
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2018-12-10 09:46:16 -07:00 |
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AurelienUoU
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7020d9b4b6
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Edit waveform generator + fix clock mapping in autochecked testbench
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2018-12-09 15:48:59 -07:00 |
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AurelienUoU
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5e94b7093d
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Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
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2018-12-08 22:57:54 -07:00 |
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Aur??Lien ALACCHI
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10866d1852
|
Correct verilog syntax error in autocheck testbench
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2018-12-08 17:40:23 -07:00 |
|
Aur??Lien ALACCHI
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d716b67e23
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Correct syntax error in autocheck testbench
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2018-12-08 17:29:56 -07:00 |
|
Aur??Lien ALACCHI
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0580d8243f
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Add Autochek testbench option
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2018-12-08 17:19:12 -07:00 |
|
Aur??Lien ALACCHI
|
4cc875a5a5
|
fix a bug in wired LUT
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2018-12-06 18:00:17 -07:00 |
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tangxifan
|
b3c1018e28
|
fixed a bug in wired LUT
|
2018-12-06 16:50:30 -07:00 |
|
Aur??Lien ALACCHI
|
eebdf7cb10
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Add possibility to choose default value for initialization
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2018-12-06 15:34:14 -07:00 |
Baudouin Chauviere
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b6bb419e1d
|
add a ModelSim option
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2018-12-06 14:13:37 -07:00 |
|
Aur??Lien ALACCHI
|
8281b7346b
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Edit auto-generated modelsim script
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2018-12-05 16:15:29 -07:00 |
|
Aur??Lien ALACCHI
|
44b7f7f3d4
|
Correct sub_modules.v generation to include decoders.v when necessary
|
2018-12-05 13:52:25 -07:00 |
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Aur??Lien ALACCHI
|
dc4accedd9
|
Add forgottent files + add parameter transmission from verilog_api.c
|
2018-12-05 11:33:14 -07:00 |
|
Aur??Lien ALACCHI
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9a8c7b391a
|
Add process for modelsim script autogeneration
|
2018-12-05 09:20:47 -07:00 |
|
Aur??Lien ALACCHI
|
75d64db0f9
|
Add verilog header sub_module.v file generation
|
2018-12-04 18:42:47 -07:00 |
|
Aur??Lien ALACCHI
|
8ac566ecc0
|
Add timing and initialization for simulation
|
2018-12-04 17:32:09 -07:00 |
|
tangxifan
|
70751551b5
|
fix a bug in wired LUT support
|
2018-11-30 21:33:31 -07:00 |
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tangxifan
|
e223868df8
|
fix bugs for wired LUTs
|
2018-11-27 12:46:30 -07:00 |
|
Aur??Lien ALACCHI
|
de2bc18bbb
|
bugs fixed for shift register benchmark
|
2018-11-26 16:58:45 -07:00 |
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tangxifan
|
861c449606
|
support wired LUT in FPGA-SPICE and FPGA-Verilog
|
2018-11-15 15:57:49 -07:00 |
|
Baudouin Chauviere
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f7d7a056da
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Modification of the fpga_spice_utils
|
2018-11-15 14:11:55 -07:00 |
|
Baudouin Chauviere
|
c81d00bb51
|
Correction of the double free bug
|
2018-11-15 13:55:16 -07:00 |
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tangxifan
|
c67ba5f58a
|
clean up codes
|
2018-09-27 14:26:08 -06:00 |
|
tangxifan
|
681cca99a4
|
fix a bug in tapbuf
|
2018-09-21 19:00:22 -06:00 |
|
tangxifan
|
d683134b12
|
rename customized vpr7 to vpr7 XML to Production
|
2018-09-17 23:10:45 -06:00 |