Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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2c1692e6dc
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[Test] Bug fix
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2021-06-29 17:54:25 -06:00 |
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tangxifan
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e58e1e86c2
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[Test] Update test case to use new shell script
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2021-01-10 11:09:10 -07:00 |
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tangxifan
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1c68e43acf
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[Test] Add new test case for registerable I/O architecture
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2021-01-10 11:00:21 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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6b48ee7f0b
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[Test] Add new test for caravel io support
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2020-11-04 20:58:40 -07:00 |
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tangxifan
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65ca53ac98
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[Test] Update test case with the new arch name
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2020-11-02 13:16:42 -07:00 |
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tangxifan
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bc00dee858
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[Test] Add test case for embedded I/O
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2020-11-02 12:28:25 -07:00 |
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tangxifan
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e4291eb27e
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[Regression Tests] Now use fixed device layout in test cases for best coverage
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2020-09-21 18:44:13 -06:00 |
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tangxifan
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50cc4dfba3
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classify regression test to dedicated categories
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2020-07-27 17:18:59 -06:00 |