Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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b72d4bd807
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[Test] Update test case for 1kbit DPRAM architectures
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2021-04-28 11:28:53 -06:00 |
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tangxifan
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5c729657ef
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[Test] Bug fix in test case for DPRAM whose width = 2
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2021-04-28 10:31:22 -06:00 |
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tangxifan
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0bec4b3f32
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[Test] Update task configuration to use proper openfpgashell script
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2021-04-27 23:34:42 -06:00 |
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tangxifan
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fdfbdc4613
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[Test] Update task configuration files to use dedicated yosys script
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2021-04-27 20:05:04 -06:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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e4291eb27e
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[Regression Tests] Now use fixed device layout in test cases for best coverage
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2020-09-21 18:44:13 -06:00 |
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tangxifan
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50cc4dfba3
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classify regression test to dedicated categories
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2020-07-27 17:18:59 -06:00 |