Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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64dcdaec61
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[Test] Update all the tasks that use counter benchmark
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2021-07-02 17:29:13 -06:00 |
Ganesh Gore
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edd5be2cae
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[CI] Added testcase for benchmark variable
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2021-07-02 12:51:34 -06:00 |
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tangxifan
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9eeec05a1f
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[Test] Bug fix
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2021-06-29 19:55:07 -06:00 |
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tangxifan
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f32ffb6d61
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[Test] Bug fix
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2021-06-29 18:51:28 -06:00 |
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tangxifan
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8046b16c15
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[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
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2021-04-21 14:04:34 -06:00 |
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tangxifan
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af0646260c
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[Test] Bug fix in pin constraints
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2021-01-19 17:44:05 -07:00 |
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tangxifan
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186f2f1968
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[Test] Use pin constraint in multi-clock test case
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2021-01-19 17:42:40 -07:00 |
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tangxifan
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e17a5cbbf2
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[Test] Rename to pin constraint to comply with libpcf requirement
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2021-01-19 15:52:51 -07:00 |
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tangxifan
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ab25e1af5f
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[Test] Add example XML for net mapping between benchmark to FPGA
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2021-01-19 09:29:21 -07:00 |
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tangxifan
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ea9d6bfe91
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[Flow] Update the design constraint file to follow bug fix in parser
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2021-01-17 10:41:01 -07:00 |
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tangxifan
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dd74f05a31
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[Test] Add repack constraints to tests
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2021-01-17 10:35:36 -07:00 |
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tangxifan
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d0e05b3575
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[Lib] Now use pb_type in design constraints instead of physical tiles
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2021-01-16 21:35:43 -07:00 |
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tangxifan
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8578c1ecac
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[Flow] Rename the design contraint file syntax
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2021-01-16 15:35:13 -07:00 |
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tangxifan
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9154cfdeec
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[Flow] Add comments for the design constraint file
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2021-01-16 15:34:01 -07:00 |
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tangxifan
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6ab0f71896
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[Test] Add an example of repack pin constraints file
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2021-01-16 14:38:39 -07:00 |
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tangxifan
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3b5394b45f
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[Test] Now use dedicated simulation settings for the 4-clock architecture
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2021-01-14 15:40:16 -07:00 |
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tangxifan
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314e458632
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[Test] Update task configuration to use post-yosys .v file in verification
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2021-01-13 15:42:45 -07:00 |
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tangxifan
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91f12071d5
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[Test] Use counter4bit in the multi-clock test
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2021-01-13 13:34:59 -07:00 |
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tangxifan
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250adb01cf
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[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
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2021-01-13 13:18:31 -07:00 |
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tangxifan
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99e2a068fb
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[Test] Add a test case for multi-clock
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2021-01-12 18:06:25 -07:00 |
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tangxifan
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43418cd76b
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[Test] Deploy pipeplined and2 to test cases
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2021-01-10 10:28:22 -07:00 |
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tangxifan
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179b0ce304
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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
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2020-11-30 18:11:47 -07:00 |
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tangxifan
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27a480b5f8
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[Test] arch name fix in the test case
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2020-11-30 17:45:54 -07:00 |
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tangxifan
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a1d3b439d3
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[Test] Add a new test case to define a global reset port from a global tile port
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2020-11-30 17:19:12 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
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485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |