tangxifan
|
1fd974d544
|
[core] fixed a bug where clock network size cannot impact global port on top module
|
2024-06-29 17:35:47 -07:00 |
|
tangxifan
|
5dd0549aed
|
[core] typo
|
2024-06-29 17:17:54 -07:00 |
|
tangxifan
|
bc2f02866d
|
[test] update testcase for 2-clk on programmable clock network
|
2024-06-29 17:17:05 -07:00 |
|
tangxifan
|
286df30947
|
[test] update clock arch xml syntax
|
2024-06-29 11:02:17 -07:00 |
|
tangxifan
|
4f787a5cfc
|
[core] add more debugging message
|
2024-06-29 10:54:08 -07:00 |
|
tangxifan
|
5fa674be24
|
[core] fixed the bug on matching global net from pcf
|
2024-06-29 10:51:45 -07:00 |
|
tangxifan
|
34fb003911
|
[core] replace width syntax with global port name
|
2024-06-29 10:46:00 -07:00 |
|
tangxifan
|
67554cb8d8
|
[test] now use correct pcf for clock network testcases
|
2024-06-29 10:04:03 -07:00 |
|
tangxifan
|
8bc37080fa
|
[core] debuggging
|
2024-06-28 23:06:21 -07:00 |
|
tangxifan
|
1c69365938
|
[core] debugging
|
2024-06-28 18:17:38 -07:00 |
|
tangxifan
|
0de3ff3eb8
|
[core] debugging
|
2024-06-28 17:16:33 -07:00 |
|
tangxifan
|
e0b9f7860b
|
[core] fixed a bug where counter for gnets are not activated
|
2024-06-28 14:10:14 -07:00 |
|
tangxifan
|
5cfd23747b
|
[core] code format
|
2024-06-28 13:47:03 -07:00 |
|
tangxifan
|
f4dd222c47
|
[test] deploy new testcases to basic reg tests
|
2024-06-28 13:45:36 -07:00 |
|
tangxifan
|
f1a4304ee7
|
[test] add new testcases for validate clock tree disable functions
|
2024-06-28 13:43:53 -07:00 |
|
tangxifan
|
ad5795bece
|
[test] add extra options to route clock rr_graph command in examples
|
2024-06-28 13:39:41 -07:00 |
|
tangxifan
|
1094af9f73
|
[doc] add new options to route clock graph
|
2024-06-28 12:38:40 -07:00 |
|
tangxifan
|
f5b6774eb0
|
[core] add code comments and fixed some bugs
|
2024-06-28 12:21:33 -07:00 |
|
tangxifan
|
53ba2f0c29
|
[core] fixed a critical bug where some switching points are missing
|
2024-06-27 15:53:17 -07:00 |
|
tangxifan
|
5a7f618f29
|
[core] debugging
|
2024-06-27 15:44:17 -07:00 |
|
tangxifan
|
f4f487099d
|
[core] syntax
|
2024-06-27 15:07:48 -07:00 |
|
tangxifan
|
4185235a69
|
[core] now clock routing is based on tree expansion. Unused part can be disconnected
|
2024-06-27 15:02:20 -07:00 |
|
tangxifan
|
e75fd57af2
|
[core] refactor codes
|
2024-06-27 12:39:18 -07:00 |
|
tangxifan
|
7892c2340c
|
[core] add a new option 'disable_unused_trees' to route clock rr graph
|
2024-06-27 12:01:54 -07:00 |
|
tangxifan
|
3fb891094b
|
[doc] add new syntax
|
2024-06-27 11:02:37 -07:00 |
|
tangxifan
|
6fceb81110
|
[core] code format
|
2024-06-27 10:19:40 -07:00 |
|
tangxifan
|
64a7a4ce26
|
[core] syntax
|
2024-06-27 10:19:14 -07:00 |
|
tangxifan
|
9ce552495a
|
[core] now internal drivers can be routed in dedicated clock network
|
2024-06-27 10:17:08 -07:00 |
|
tangxifan
|
53c155c02b
|
Merge pull request #1731 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-27 09:52:57 -07:00 |
github-actions[bot]
|
1f4fda25eb
|
Updated Patch Count
|
2024-06-27 16:44:38 +00:00 |
|
tangxifan
|
39e0c1b635
|
Merge pull request #1730 from lnis-uofu/dependabot/submodules/yosys-07daf61
Bump yosys from `1288166` to `07daf61`
|
2024-06-27 09:44:16 -07:00 |
dependabot[bot]
|
ec85bfc704
|
Bump yosys from `1288166` to `07daf61`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `1288166` to `07daf61`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](1288166f7a...07daf61ae6)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-27 06:41:45 +00:00 |
|
tangxifan
|
ac1ad52795
|
[core] code format
|
2024-06-26 22:47:29 -07:00 |
|
tangxifan
|
5d0b0b9a8c
|
[core] now global nets mapping are applied to clock routing
|
2024-06-26 22:46:12 -07:00 |
|
tangxifan
|
d5d9531eec
|
[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
|
2024-06-26 21:52:45 -07:00 |
|
tangxifan
|
cab649893b
|
[core] update clock architecture
|
2024-06-26 18:06:39 -07:00 |
|
tangxifan
|
59be95b227
|
[core] code format
|
2024-06-26 17:58:26 -07:00 |
|
tangxifan
|
59404e5487
|
[core] add verbose output
|
2024-06-26 17:55:23 -07:00 |
|
tangxifan
|
576a861b8d
|
[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
|
2024-06-26 17:54:31 -07:00 |
|
tangxifan
|
3efa97b84e
|
[core] support coordinate on clock taps
|
2024-06-26 17:40:11 -07:00 |
|
tangxifan
|
3b25e42720
|
[lib] syntax
|
2024-06-26 15:51:00 -07:00 |
|
tangxifan
|
381a8cb535
|
[lib] clock tap syntax are reworked. Support region, single, all and from/to ports
|
2024-06-26 15:41:56 -07:00 |
|
tangxifan
|
bd05bc4c24
|
Merge pull request #1729 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-25 20:16:17 -07:00 |
|
github-actions[bot]
|
3ebaaa700e
|
Updated Patch Count
|
2024-06-26 01:31:49 +00:00 |
|
tangxifan
|
52e2fed5f4
|
Merge pull request #1726 from lnis-uofu/xt_ci
Use a new version of cancel-previous-flow due to node16 deprecation
|
2024-06-25 18:31:31 -07:00 |
|
tangxifan
|
c07e35136b
|
[ci] now use download-artifact v4
|
2024-06-25 16:46:33 -07:00 |
|
tangxifan
|
ec1ad94d4a
|
[doc] add syntax about internal drivers
|
2024-06-25 13:06:47 -07:00 |
|
tangxifan
|
c99178f350
|
[test] fixed a bug on pin locations
|
2024-06-25 12:34:52 -07:00 |
|
tangxifan
|
4640e74e7e
|
[core] code format
|
2024-06-25 12:25:16 -07:00 |
|
tangxifan
|
66af73e91e
|
[lib] now accept reset and set in programmable clock network
|
2024-06-25 12:24:46 -07:00 |