Commit Graph

7653 Commits

Author SHA1 Message Date
tangxifan 6492d43a01 [test] add a new test to validate perimeter cb using global tile clock 2024-07-08 11:29:20 -07:00
tangxifan 48ae3691c4 [test] typo 2024-07-08 10:57:54 -07:00
tangxifan 5c9c4d93c5 [core] typo 2024-07-08 10:46:47 -07:00
tangxifan cdd477ad80 [core] remove restrictions on cb clock nodes 2024-07-08 10:14:39 -07:00
tangxifan 8449da0143 [core] typo 2024-07-07 23:36:13 -07:00
tangxifan ff56139a53 [test] debugging 2024-07-07 23:07:51 -07:00
tangxifan b0851a6299 [test] debugging 2024-07-07 23:05:37 -07:00
tangxifan 686cd761b7 [test] debugging 2024-07-07 22:48:21 -07:00
tangxifan 57a378ae59 [test] typo 2024-07-07 22:35:14 -07:00
tangxifan f784e58383 [test] typo 2024-07-07 22:33:45 -07:00
tangxifan 1a5e2392fc [test] add a new testcase to validate clock network when perimeter cb is on 2024-07-07 22:32:13 -07:00
tangxifan db12532eb8 [test] typo 2024-07-07 21:41:39 -07:00
tangxifan 7996de3fe6 [core] now support perimeter cb in programmable clock network arch 2024-07-07 14:57:05 -07:00
tangxifan 4da5150a26 [doc] update for bottom-left tile organization 2024-07-07 14:20:26 -07:00
tangxifan 439de61fd0 [test] fixed a bug on ecb support 2024-07-07 14:00:11 -07:00
tangxifan 91f8bb5841 [doc] update figures for ecb 2024-07-07 13:40:01 -07:00
tangxifan 201b2555e5 [test] code format 2024-07-06 12:15:08 -07:00
tangxifan 703cbddc9e [core] code format 2024-07-06 12:14:57 -07:00
tangxifan 43ca3ec747 [test] make arch pin loc for spread for perimeter cb validation 2024-07-06 12:11:31 -07:00
tangxifan 6024e35f89 [core] fixed a bug 2024-07-05 18:50:14 -07:00
tangxifan 1f7fbfef64 [core] fixed a bug on inter-tile connections in top module 2024-07-05 18:19:22 -07:00
tangxifan e95b264965 [core] debugging 2024-07-05 18:08:48 -07:00
tangxifan a46820b7c1 [core] add a new test for bottom-left tile grouping 2024-07-05 18:00:37 -07:00
tangxifan cca9fb4756 [core] fixed a bug on bottom left tile organization 2024-07-05 17:55:19 -07:00
tangxifan 46d916f0a0 [core] fixed the bugs in fabric tile build-up 2024-07-05 16:59:08 -07:00
tangxifan 5e89b950ed [lib] update vtr 2024-07-05 13:41:38 -07:00
tangxifan a41f437109 [core] now netlist look ok 2024-07-05 12:36:47 -07:00
tangxifan 283aa3a1c9 [core] debug 2024-07-05 12:21:17 -07:00
tangxifan f2506598a9 [lib] update vtr 2024-07-05 12:20:49 -07:00
tangxifan 36c0cfe645 [lib] update vtr 2024-07-05 12:14:14 -07:00
tangxifan 46e3b4b071 [core] debug 2024-07-05 11:50:41 -07:00
tangxifan e5d75cc51e [lib] update vtr 2024-07-05 11:47:04 -07:00
tangxifan fdbc427f70 [core] debug 2024-07-05 11:17:05 -07:00
tangxifan f6adca1545 [core] fixed a bug 2024-07-05 11:02:01 -07:00
tangxifan ba1482f533 [lib] update vtr 2024-07-05 11:01:31 -07:00
tangxifan b6e89b8943 [lib] update vtr 2024-07-05 10:52:35 -07:00
tangxifan 1dc602a849 [core] syntax 2024-07-05 10:38:26 -07:00
tangxifan 266c2686d4 [core] adapt new gsb coordinate system 2024-07-05 10:32:33 -07:00
tangxifan 47ba57a27c [lib] update vtr 2024-07-05 10:16:50 -07:00
tangxifan fe73e03c69 [test] changing arch 2024-07-04 21:31:43 -07:00
tangxifan 4064c29d49 [test] updating arch for perimeter cb 2024-07-04 21:23:15 -07:00
tangxifan 5865aebf93 [test] add new arch 2024-07-04 21:12:26 -07:00
tangxifan 1f8c2436ef [core] now constant_undriven_inputs are force to enable when perimeter_cb is selected 2024-07-04 20:46:38 -07:00
tangxifan 72ee39f178 [core] add new command line option 'constant_undriven_inputs' 2024-07-04 20:39:02 -07:00
tangxifan 4e21bbb3f1 [core] now support constant undriven local wires in verilog writer 2024-07-04 20:32:56 -07:00
tangxifan 1dd03d0fdd [core] on a new feature to connect undriven pins to ground 2024-07-04 18:34:39 -07:00
tangxifan 93af72f1e3 [lib] update vtr 2024-07-04 14:57:36 -07:00
tangxifan 6d798897fd [lib] update vtr 2024-07-04 14:46:57 -07:00
tangxifan f560fb8381 [core] more verbose 2024-07-04 14:27:17 -07:00
tangxifan a8850d4f0f [core] now verbose mode is applicable to more build top module cb instances 2024-07-04 14:22:30 -07:00