3 Commits

Author	SHA1	Message	Date
tangxifan	40663f956c	[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability	2022-09-19 21:55:15 -07:00
tangxifan	da3f9ccb80	[Test] Truncating counter designs in each task	2022-02-14 12:22:19 -08:00
tangxifan	0268814fc6	[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests	2022-02-14 12:20:56 -08:00