4 Commits

Author	SHA1	Message	Date
tangxifan	c2d8fa00ba	add rr_block unique_side_module verilog generation	2019-06-04 17:47:40 -06:00
tangxifan	ea8c36ce6e	upgrade Verilog SB generator using the RRSwitchBlock	2019-05-23 17:37:39 -06:00
AurelienUoU	42f20eda60	Add the user matching for internal register in formal verification script generation	2019-05-03 10:24:02 -06:00
tangxifan	46d44fa42a	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00