tangxifan
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c2d8fa00ba
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add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
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tangxifan
|
ea8c36ce6e
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upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
|
tangxifan
|
b185a17359
|
add routing_channel unique module generation
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2019-05-20 22:33:17 -06:00 |
Baudouin Chauviere
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2019840d7c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
AurelienUoU
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42f20eda60
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Add the user matching for internal register in formal verification script generation
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2019-05-03 10:24:02 -06:00 |
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tangxifan
|
46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |