4 Commits

Author	SHA1	Message	Date
tangxifan	29104b6fa5	rework on the circuit model ports and start prototyping mux Verilog generation	2019-08-20 15:24:53 -06:00
tangxifan	a7ac1e4980	remame methods in circuit_library	2019-08-20 15:24:53 -06:00
tangxifan	c7526cb43c	memory sanitized	2019-08-13 14:19:40 -06:00
tangxifan	ef4d15df4e	reorganize the libarchfpga repository	2019-08-13 13:37:35 -06:00