tangxifan
|
0db4ef62e8
|
[test] add a new test for tile-based fabric: using preconfig testbenches
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2023-07-25 15:48:14 -07:00 |
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tangxifan
|
523cf83cc9
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[test] disable pnr writer in test cases
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2023-07-25 15:39:25 -07:00 |
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tangxifan
|
82fe63297a
|
[test] add a new test for top-left tile grouping
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2023-07-19 11:22:36 -07:00 |
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tangxifan
|
270d6f933b
|
[test] add a new testcase to validate mock wrapper
|
2023-06-26 15:26:50 -07:00 |
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tangxifan
|
919d6d8608
|
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
|
2023-06-25 22:49:51 -07:00 |
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tangxifan
|
962ba67e36
|
[test] adding new tests to validate fpga core wrapper naming rules
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2023-06-23 14:47:21 -07:00 |
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tangxifan
|
fd8f371d85
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[test] add missing file
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2023-06-19 16:44:11 -07:00 |
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tangxifan
|
efc9bf9907
|
[test] added new test case to validate bitstream generation
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2023-06-19 12:40:37 -07:00 |
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tangxifan
|
97b089ae3c
|
[test] added new testcases to validate fpga core wrapper
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2023-06-18 21:01:37 -07:00 |
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tangxifan
|
ac31a20376
|
[test] now bypass clock routing in default example
|
2023-06-08 13:44:22 -07:00 |
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tangxifan
|
27b8007d1b
|
[test] rework pcf support testcase for mock wrapper
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2023-05-27 12:45:29 -07:00 |
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tangxifan
|
b6c90eb99a
|
[core] fixed several bugs which causes bgf and pcf support in mock wrapper failed
|
2023-05-27 12:13:16 -07:00 |
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tangxifan
|
e1feebc96d
|
[core] fixing bugs on pcf and bgf support for mock efpga wrapper
|
2023-05-26 21:54:08 -07:00 |
|
tangxifan
|
77be053966
|
[test] mock wrapper does not need bitstream forcing
|
2023-05-26 18:50:54 -07:00 |
|
tangxifan
|
7fbe567d4c
|
[test] add more testcases
|
2023-05-25 20:24:02 -07:00 |
|
tangxifan
|
7da7d03db5
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[script] add example script for mock wrapper
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2023-05-25 19:59:14 -07:00 |
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tangxifan
|
40598d25a3
|
[core] fixed a bug which causes multi-clock programmable network failed in routing
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2023-04-20 15:05:45 +08:00 |
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tangxifan
|
fba0a83679
|
[test] debugging 2-clock network
|
2023-04-20 14:44:01 +08:00 |
|
tangxifan
|
03cb664049
|
[test] now clock network example script supports multiple clocks
|
2023-04-20 10:56:36 +08:00 |
|
tangxifan
|
7d333b3669
|
[test] add a new test for clock network: validate full testbench is working
|
2023-04-20 10:36:08 +08:00 |
|
tangxifan
|
780dec6b1b
|
[test] add a new test to validate the programmable clock arch
|
2023-02-28 21:46:57 -08:00 |
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tangxifan
|
e974e5ddf7
|
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
|
2023-01-18 18:31:36 -08:00 |
|
tangxifan
|
758cc7a089
|
[test] debugging
|
2023-01-15 11:44:48 -08:00 |
|
tangxifan
|
f6f153ace4
|
[test] debugging
|
2023-01-11 17:06:31 -08:00 |
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tangxifan
|
d5ebbeea9a
|
[test] adding a new test to show how to automate generation of bus group files
|
2023-01-11 16:59:54 -08:00 |
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tangxifan
|
54c3b965f2
|
[script] fixed a bug
|
2023-01-01 17:19:11 -08:00 |
|
tangxifan
|
3c8e157d7b
|
[script] rename and fix typo
|
2023-01-01 17:13:23 -08:00 |
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tangxifan
|
83d7ff56e1
|
[script] add dedicated testcase for source commands
|
2023-01-01 17:04:24 -08:00 |
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tangxifan
|
cdec0cf28c
|
[script] add a custom variable to specify the path to openfpga shell script
|
2023-01-01 16:51:21 -08:00 |
|
tangxifan
|
c50daf273c
|
[script] add example script for using source command
|
2023-01-01 16:50:10 -08:00 |
|
tangxifan
|
d7a95a8ec2
|
[script] fixed some bugs
|
2022-12-30 18:30:52 -08:00 |
|
tangxifan
|
6973e9fb98
|
[script] add an example script for vpr standalone calls
|
2022-12-30 18:23:14 -08:00 |
|
tangxifan
|
609e096b1a
|
[test] added a new test to validate explicit port direction in pin table support
|
2022-10-17 15:25:19 -07:00 |
|
tangxifan
|
7f67794787
|
[arch]add new arch to test
|
2022-10-13 10:54:40 -07:00 |
|
tangxifan
|
088ff1a474
|
[script] fixed a bug
|
2022-09-29 16:27:03 -07:00 |
|
tangxifan
|
a3e7133d63
|
Merge branch 'master' into wire_lut_test
|
2022-09-29 16:02:18 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
3f8e2ade2e
|
[script] update missing scripts required by pb_pin_fixup test cases
|
2022-09-29 13:39:46 -07:00 |
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tangxifan
|
49fa783914
|
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
|
2022-09-29 10:45:27 -07:00 |
|
tangxifan
|
eaa0b5588a
|
[test] fixed a bug in pin constrain examples
|
2022-09-21 14:10:12 -07:00 |
|
tangxifan
|
baac236ed7
|
[test] fixed a bug in example scripts due to the changes on vpr options
|
2022-09-21 10:52:49 -07:00 |
|
tangxifan
|
d0b018ad6e
|
[script] mismatches in vpr options due to upgrade
|
2022-09-21 09:27:26 -07:00 |
|
tangxifan
|
b630d60b7e
|
[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
|
2022-09-20 14:14:18 -07:00 |
|
tangxifan
|
37c5056d6a
|
[test] now use a fixed routing channel width for quicklogic tests
|
2022-09-20 12:25:40 -07:00 |
|
tangxifan
|
846ca26311
|
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
|
2022-09-20 12:08:24 -07:00 |
|
tangxifan
|
63cb8d589d
|
[test] fixed a typo
|
2022-09-19 23:14:15 -07:00 |
|
tangxifan
|
d9bd0a6cf3
|
[test] disable clustering-routing result sync-up when calling vpr in example scripts
|
2022-09-19 20:52:04 -07:00 |
|
tangxifan
|
fca1c82388
|
[test] disable clustering and routing sync when using VPR
|
2022-09-19 20:33:35 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
|
tangxifan
|
1c2192a87d
|
[engine] fixed a few bugs
|
2022-09-12 16:50:32 -07:00 |