tangxifan
|
c63cee458b
|
[script] adapt code format for python
|
2024-04-10 12:58:05 -07:00 |
|
tangxifan
|
2bd60dad11
|
[script] now timing extraction focus on the last found results
|
2023-12-12 14:10:13 -08:00 |
|
tangxifan
|
592e2e310c
|
[script] typo
|
2023-12-12 13:45:23 -08:00 |
|
tangxifan
|
f689ef7654
|
[script] format
|
2023-12-12 13:15:03 -08:00 |
|
tangxifan
|
4c0f6e2273
|
[script] syntax
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2023-12-12 13:14:47 -08:00 |
|
tangxifan
|
1a4aaaf759
|
[script] update openfpga flow to support args for default tool path
|
2023-12-12 10:00:50 -08:00 |
Ganesh Gore
|
a6263c44af
|
Updated format
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2023-02-11 18:12:04 -07:00 |
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tangxifan
|
9d8f4c1664
|
[script] format python codes
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2022-11-21 14:21:31 -08:00 |
|
tangxifan
|
abee802830
|
[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers
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2022-09-20 13:46:30 -07:00 |
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tangxifan
|
9ea4a7c90f
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[script] fixed a bug
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2022-08-01 19:18:41 -07:00 |
|
tangxifan
|
55c7b75ab6
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[script] even when power analysis mode is turned off, if users define a act file, still use it
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2022-08-01 18:13:57 -07:00 |
root
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0da44ad1fc
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[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
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2022-08-02 08:02:28 +08:00 |
|
tangxifan
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1d3c9ff192
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[Script] Adapt python scripts to support include directory
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2022-02-01 13:55:25 -08:00 |
Aram Kostanyan
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588ee14920
|
Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
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fb2e4377c8
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Added missing changes from previous commit.
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2022-01-17 19:42:40 +05:00 |
|
Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
Awais Abbas
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fc52a4696c
|
Yosys only support added in OpenFPGA
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2022-01-06 14:44:11 +05:00 |
|
Aram Kostanyan
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a355977420
|
Adding Yosys+Verific support.
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2021-10-29 18:34:27 +05:00 |
Christophe Alexandre
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c42acec81e
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Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
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2021-10-18 10:45:35 +00:00 |
|
Christophe Alexandre
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c3dd704bf3
|
Fixing typo in run_fpga_flow.py
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2021-10-18 09:13:42 +00:00 |
|
Christophe Alexandre
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d411967159
|
Fixing small typo in run_fpga_flow.py
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2021-10-15 10:01:12 +00:00 |
|
tangxifan
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7119075253
|
[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
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2021-06-29 15:52:42 -06:00 |
|
tangxifan
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e1f8b252b1
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-16 20:05:21 -06:00 |
|
tangxifan
|
090f483a11
|
[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
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2021-03-16 16:45:57 -06:00 |
|
tangxifan
|
b42541d84e
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[Flow] Support multiple iterations in rewriting yosys scripts
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2021-03-10 14:10:35 -07:00 |
|
tangxifan
|
aafd87c3f9
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[Flow] Update flow-run to support custom yosys rewrite scripts
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2021-03-10 11:36:29 -07:00 |
|
tangxifan
|
131643dcc0
|
[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
|
2021-03-08 21:08:55 -07:00 |
|
ganeshgore
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b860722893
|
Fixed parameter ys_rewrite_params name bug
|
2021-03-08 10:34:39 -07:00 |
|
ganeshgore
|
52de55e7eb
|
Merge branch 'master' into ganesh_dev
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2021-03-08 10:15:06 -07:00 |
|
Ganesh Gore
|
7a35811430
|
[Flow] Yosys rewrite support
|
2021-03-08 00:35:47 -07:00 |
|
Ganesh Gore
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67cd9a69b7
|
[Flow] Extended yosys variable subtitution
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2021-03-08 00:21:07 -07:00 |
Lalit Sharma
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6a1ce01084
|
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
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2021-03-07 22:02:11 -08:00 |
|
Lalit Sharma
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0cbad747a1
|
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
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2021-03-04 01:10:47 -08:00 |
|
Lalit Sharma
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817729ac86
|
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
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2021-03-01 22:31:15 -08:00 |
|
tangxifan
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a819375f69
|
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
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2021-02-16 16:53:13 -07:00 |
Tarachand Pagarani
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3a587f663a
|
copy yosys output file in case power analysis setting is off
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2021-02-15 02:36:02 -08:00 |
|
Ganesh Gore
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6cdc31f073
|
[Flow] ACE is optional duign flow script
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2021-02-03 19:07:48 -07:00 |
|
Ganesh Gore
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df4a397470
|
[Cleanup] Removed deadcode
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2021-02-03 10:35:14 -07:00 |
|
ganeshgore
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289d9d2169
|
[Bugfix] Honors yosys_tmpl parameter in flow script
|
2020-12-03 12:24:24 -07:00 |
|
ganeshgore
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59bd7d0f18
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[Flow] Changed substitute to safe_sustitute option
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2020-11-25 22:09:36 -07:00 |
|
ganeshgore
|
fefba0db59
|
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
|
2020-11-25 17:29:53 -07:00 |
|
ganeshgore
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1554f583b7
|
[Flow] Now support explicit variable file for task
|
2020-11-25 17:22:41 -07:00 |
|
tangxifan
|
521accdc88
|
Merge pull request #104 from lukefahr/disp_fix
FLOW: fixed display flag
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2020-10-07 09:54:06 -06:00 |
|
tangxifan
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7b12c28e4f
|
Merge pull request #102 from lukefahr/blif_bug
Fixed blif formatting bug
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2020-10-06 20:05:02 -06:00 |
Andrew Lukefahr
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33bbe0ec48
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FLOW: fixed display flag
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2020-10-06 20:52:28 -04:00 |
|
Andrew Lukefahr
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d68427e47b
|
Fixed blif formatting bug
|
2020-10-06 20:46:50 -04:00 |
|
Andrew Lukefahr
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2d92a1f1af
|
Edits to enable basic run_fpga_flow.py
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2020-10-02 10:18:10 -04:00 |
|
ganeshgore
|
747c062f86
|
BugFix : Flow script accepts extra OpenFPGA arguments
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2020-07-27 18:10:43 -06:00 |
|
ganeshgore
|
3b6cd885f3
|
BugFix: Fixed yosys_vpr with openFPGA_Shell
|
2020-07-22 11:57:04 -06:00 |
|
ganeshgore
|
41585436c8
|
Added external_fabric_key_file key
|
2020-06-12 15:37:12 -06:00 |