tangxifan
|
7b4f06ed7d
|
[test] validate mux2 at last stage
|
2024-09-18 17:40:13 -07:00 |
|
tangxifan
|
bdc13e491e
|
[arch] adding openfpga arch for ecb
|
2024-05-20 12:04:52 -07:00 |
|
tangxifan
|
02a5057449
|
[arch] add openfpga arch example using subtile; updated documentation
|
2023-05-03 15:20:49 +08:00 |
|
tangxifan
|
02e964b16f
|
[test] add a new test case for ccffv2
|
2023-04-22 15:41:19 +08:00 |
|
tangxifan
|
9222d085cd
|
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
|
2023-01-13 22:04:56 -08:00 |
|
tangxifan
|
5e23be19a5
|
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
|
2022-09-20 18:07:31 -07:00 |
|
tangxifan
|
812af4f722
|
[arch] add arch that supports negative edge triggered flip-flop
|
2022-05-09 16:32:01 +08:00 |
|
tangxifan
|
c8da85cc24
|
[Doc] Update naming convention for OpenFPGA architecture files
|
2022-03-20 10:51:55 +08:00 |
|
tangxifan
|
7598455497
|
[Doc] Update naming convention for architecture files
|
2022-01-02 19:51:09 -08:00 |
|
tangxifan
|
64294ae4eb
|
[Doc] Update README for architecture files due to new architecture features
|
2021-04-16 19:25:54 -06:00 |
|
tangxifan
|
2f1aceda67
|
[Doc] Update documentation about architecture naming rules
|
2021-01-12 18:01:24 -07:00 |
|
tangxifan
|
f21d22f691
|
[Doc] Update README for new architectures
|
2021-01-10 10:54:59 -07:00 |
|
tangxifan
|
17070c6405
|
[Doc] Update README in openfpga arch directory for native fracturable LUT design
|
2020-11-25 22:19:20 -07:00 |
|
tangxifan
|
fefcd88f14
|
update openfpga architecture README for power-gating
|
2020-07-22 21:55:59 -06:00 |
|
tangxifan
|
73e75bf456
|
add readme for OpenFPGA architecture naming
|
2020-07-01 10:27:21 -06:00 |