4 Commits

Author	SHA1	Message	Date
tangxifan	5937ffc809	add XML parsing for buffer/pass-gate-logic -related properties	2020-01-14 15:44:24 -07:00
tangxifan	56113e1aab	adding XML parsing for design tech of circuit model	2020-01-14 14:10:00 -07:00
tangxifan	2692d0fc35	adding XML parsing for SPICE and Verilog netlist for each circuit model	2020-01-14 08:45:27 -07:00
tangxifan	82d83ddceb	reorganized the read XML openfpga arch	2020-01-14 08:33:48 -07:00