Commit Graph

5522 Commits

Author SHA1 Message Date
tangxifan 419a3a1e46 [arch] fixed a bug 2022-09-08 16:53:52 -07:00
tangxifan 7fe240e199 [vpr] fixed a bug when parsing conventional pin loc 2022-09-08 16:53:00 -07:00
tangxifan 122a323668 [arch] fixed bugs 2022-09-08 16:50:33 -07:00
tangxifan 765712a263 [vpr] fixed a bug when parsing instances 2022-09-08 16:47:28 -07:00
tangxifan d76f3e3b6c [test] fixed the bug 2022-09-08 16:34:23 -07:00
tangxifan 218e6d0a47 [arch] fixed syntax errors 2022-09-08 16:31:52 -07:00
tangxifan a840aeea7a [test] add a new test to validate custom I/O location syntax and deploy to basic regression tests 2022-09-08 16:27:11 -07:00
tangxifan b1fad0b4e5 [arch] add an example architecture to show the use extended syntax 2022-09-08 16:19:21 -07:00
tangxifan c71b533e9f [vpr] syntax 2022-09-08 16:04:25 -07:00
tangxifan b943d79092 [vpr] now support the definition of subtile in custom pin location, such io[3:4].a2f[0:0] 2022-09-08 15:57:08 -07:00
tangxifan cd112ce703
Merge branch 'master' into vtr_upgrade 2022-09-08 09:25:37 -07:00
tangxifan 1073c3306b
Merge pull request #770 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2022-09-07 17:05:00 -07:00
github-actions[bot] 89d5119c01 Updated Patch Count 2022-09-08 00:03:40 +00:00
tangxifan f74f1a6603 [engine] update vtr 2022-09-07 16:24:03 -07:00
tangxifan 148bf5e830 [engine] update vtr 2022-09-07 16:20:13 -07:00
tangxifan e5c7a3df9f [engine] syntax 2022-09-07 15:51:54 -07:00
tangxifan a81de4efed [engine] update vtr 2022-09-07 15:10:17 -07:00
tangxifan 56619f9a47 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-07 15:04:05 -07:00
Ganesh Gore 65d7f592c9
Merge pull request #766 from lnis-uofu/rr_gsb_mirror
Now switch_id is no longer a metric to fail GSB mirrorable functions but circuit model is.
2022-09-06 22:58:37 -06:00
tangxifan 3e4bc985fe Merge branch 'rr_gsb_mirror' of github.com:lnis-uofu/OpenFPGA into rr_gsb_mirror 2022-09-07 11:57:15 +08:00
tangxifan 8d09773e65 [engine] remove unnecessary checks from sb mirror checker 2022-09-07 11:55:08 +08:00
tangxifan 5a47f00708
Merge branch 'master' into rr_gsb_mirror 2022-09-06 20:21:03 -07:00
tangxifan 164a788ca3
Merge pull request #768 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2022-09-06 18:08:57 -07:00
github-actions[bot] 8382416931 Updated Patch Count 2022-09-07 00:15:01 +00:00
tangxifan b7acd6aabc
Merge branch 'master' into rr_gsb_mirror 2022-09-06 17:00:42 -07:00
tangxifan 5489f19bce
Merge pull request #767 from lnis-uofu/large_no_ts_test
Expand the no_time_stamp test case to bigger layout size
2022-09-06 17:00:29 -07:00
tangxifan 477e2119d7 [test] remove abs paths in golden outputs without time stamps 2022-09-06 15:24:43 -07:00
tangxifan 93ab992187 [test] update golden outputs without time stamps 2022-09-06 14:59:00 -07:00
tangxifan 561d0a6545 [test] add more test case to track golden outputs for representative fpga sizes 2022-09-06 14:04:23 -07:00
tangxifan e748c7697d [engine] update code comments 2022-09-06 13:51:29 -07:00
tangxifan eab3580f79 [engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity 2022-09-06 13:40:29 -07:00
tangxifan 59440082ed [engine] fixed some syntax errors 2022-09-06 11:55:40 -07:00
tangxifan 2f84ce5955 [engine] now move rr_gsb mirror function outside the class, because of the circuit_lib should be used 2022-09-06 11:48:21 -07:00
tangxifan 409753db81
Merge branch 'master' into vtr_upgrade 2022-09-02 17:43:19 -07:00
tangxifan 85532dd129
Merge pull request #763 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2022-09-02 17:42:54 -07:00
github-actions[bot] 462049eb0b Updated Patch Count 2022-09-03 00:02:20 +00:00
tangxifan b26b2d0ed0
Merge branch 'master' into vtr_upgrade 2022-09-02 10:05:23 -07:00
tangxifan b9c33bf9bc
Merge pull request #762 from lnis-uofu/win32-build-02-sep-2022
add <array> declaration to fix gcc error
2022-09-02 09:54:42 -07:00
coolbreeze413 04abd1a36f add <array> declaration to fix gcc error 2022-09-02 19:26:28 +05:30
tangxifan 9e1abf5898
Merge branch 'master' into vtr_upgrade 2022-09-01 21:39:14 -07:00
tangxifan c81259e11c
Merge pull request #760 from lnis-uofu/bitstream_encoding
Bitstream encoding - Resolve the limitation in support large FPGA devices using memory bank protocols
2022-09-01 21:37:20 -07:00
tangxifan 98a59a01ba
Merge branch 'master' into bitstream_encoding 2022-09-01 20:34:51 -07:00
tangxifan c48f750f86 [test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit 2022-09-01 20:10:29 -07:00
tangxifan d3f08a893c [engine] now frame view will not build nets for configuration bus 2022-09-01 20:02:00 -07:00
tangxifan d8f81694b0
Merge pull request #761 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2022-09-01 17:47:37 -07:00
github-actions[bot] 99e7daf06d Updated Patch Count 2022-09-02 00:04:32 +00:00
tangxifan 001367ea41 [engine] syntax 2022-09-01 16:40:17 -07:00
tangxifan 1f5e4d4215 [engine] update fabric bitstream implementation 2022-09-01 16:29:42 -07:00
tangxifan ea6f609181 [engine] fixing a bug in fabric bitstream encoding 2022-09-01 16:28:17 -07:00
tangxifan c691eb0e95
Merge branch 'master' into vtr_upgrade 2022-09-01 15:54:14 -07:00