tangxifan
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fd1c4039d3
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[test] typo
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2023-03-02 21:37:24 -08:00 |
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tangxifan
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02b50e3464
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[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
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2023-03-02 21:33:32 -08:00 |
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tangxifan
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b9f7c72a96
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[test] fixed some bugs in arch
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2023-03-02 18:16:59 -08:00 |
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tangxifan
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780dec6b1b
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[test] add a new test to validate the programmable clock arch
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2023-02-28 21:46:57 -08:00 |
Ganesh Gore
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f7c710e95e
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renamed yosys_vpr_template fabric_netlist_gen_template
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2023-02-11 18:33:06 -07:00 |
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Ganesh Gore
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b2bdfb7475
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Strip down task
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2023-02-11 18:32:06 -07:00 |
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Ganesh Gore
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b71a1014e8
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renamed vpr_blif_template to fabric_verification_template
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2023-02-11 18:29:21 -07:00 |
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Ganesh Gore
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6a48f1eb05
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Updated demo projects
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2023-02-11 18:24:20 -07:00 |
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tangxifan
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d1e951e52e
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[test] debugging
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2023-01-24 17:57:34 -08:00 |
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tangxifan
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f964c9ed67
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[test] debug
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2023-01-24 15:48:57 -08:00 |
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tangxifan
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8174f53796
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[test] deploy new test to fpga bitstream regression
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2023-01-24 15:42:01 -08:00 |
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tangxifan
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fec84d76d1
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[arch] adding tech lib;
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2023-01-24 15:22:34 -08:00 |
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tangxifan
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d60d0540da
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[test] adding a new test case to validate the bitstream overloading for DSP blocks
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2023-01-24 14:58:52 -08:00 |
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tangxifan
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f586229b97
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[test] enable rst_on_lut benchmark
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2023-01-18 19:45:41 -08:00 |
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tangxifan
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b7a66705e0
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[test] now use yosys_vpr flow; add rst_on_lut benchmark
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2023-01-18 19:42:50 -08:00 |
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tangxifan
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e974e5ddf7
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[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
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2023-01-18 18:31:36 -08:00 |
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tangxifan
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03273371c0
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[test] add a new test to validate local reset
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2023-01-18 18:17:14 -08:00 |
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tangxifan
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2c9593c1d4
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[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
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2023-01-15 13:09:40 -08:00 |
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tangxifan
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13aed6fff5
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[test] still commment verification out
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2023-01-15 12:17:59 -08:00 |
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tangxifan
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758cc7a089
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[test] debugging
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2023-01-15 11:44:48 -08:00 |
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tangxifan
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14bb76ec87
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[test] remove verification steps for new test but leave a todo
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2023-01-14 23:06:54 -08:00 |
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tangxifan
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9222d085cd
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[test] now use local clock as one of the pins in a clock bus, but connected to global routing
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2023-01-13 22:04:56 -08:00 |
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tangxifan
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26f71656de
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[test] update pin constraints
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2023-01-13 21:12:18 -08:00 |
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tangxifan
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93107c752a
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[test] updating test case
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2023-01-13 19:53:15 -08:00 |
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tangxifan
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1353577351
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[test] added a new test to validate locally generated clocks
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2023-01-13 16:45:30 -08:00 |
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tangxifan
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c7dc3ce7dc
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[test] pass
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2023-01-11 17:10:29 -08:00 |
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tangxifan
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f6f153ace4
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[test] debugging
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2023-01-11 17:06:31 -08:00 |
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tangxifan
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d5ebbeea9a
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[test] adding a new test to show how to automate generation of bus group files
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2023-01-11 16:59:54 -08:00 |
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tangxifan
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83d7ff56e1
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[script] add dedicated testcase for source commands
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2023-01-01 17:04:24 -08:00 |
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tangxifan
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d7a95a8ec2
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[script] fixed some bugs
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2022-12-30 18:30:52 -08:00 |
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tangxifan
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56a3e6e463
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[test] reduce test size
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2022-12-30 18:28:17 -08:00 |
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tangxifan
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ae11a4fbf2
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[test] add a new test case
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2022-12-30 18:25:15 -08:00 |
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tangxifan
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12d114bbae
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[test] hit the bug of tileable rr_graph skip it
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2022-11-05 10:52:04 -07:00 |
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tangxifan
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dc24e41c6b
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[test] relax minW for counter128, as VPR's router degrades in routability
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2022-11-03 19:48:13 -07:00 |
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tangxifan
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513f7800aa
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[test] update golden outputs for no_cout_in_gsb testcase
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2022-11-03 17:51:51 -07:00 |
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tangxifan
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a88bc2d4de
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[test] update golden outputs for device4x4
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2022-11-03 17:51:08 -07:00 |
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tangxifan
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5f74367c2e
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[test] update golden for device1x1 no time stamp netlists
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2022-11-03 17:48:40 -07:00 |
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tangxifan
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40f1f2fbc6
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[test] update golden results for iwls
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2022-10-21 20:28:10 -07:00 |
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tangxifan
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04286508c8
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[test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back
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2022-10-21 20:26:56 -07:00 |
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tangxifan
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00a485cbeb
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[test] add missing file
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2022-10-17 19:44:25 -07:00 |
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tangxifan
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609e096b1a
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[test] added a new test to validate explicit port direction in pin table support
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2022-10-17 15:25:19 -07:00 |
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tangxifan
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8b00bfdff9
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[test] replace hardcoded paths in task config files with relative paths
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2022-10-17 11:55:57 -07:00 |
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tangxifan
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aa78981e37
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[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
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2022-10-17 11:18:21 -07:00 |
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tangxifan
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b0be27b384
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[test] add repack design constraints files
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2022-10-13 11:22:48 -07:00 |
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tangxifan
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7f67794787
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[arch]add new arch to test
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2022-10-13 10:54:40 -07:00 |
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tangxifan
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ab53f88c2b
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[test] now use a fixed device layout for the single-mode LUT design testcase
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2022-10-04 10:05:22 -07:00 |
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tangxifan
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4eaecde0b9
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[test] add golden netlists to ensure no cout in gsb
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2022-10-01 11:03:13 -07:00 |
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tangxifan
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78f30cf072
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[test] add a new test to track the golden netlists where cout is not in GSB
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2022-09-30 15:38:27 -07:00 |
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tangxifan
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0565ca7aca
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[script] add missing files
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2022-09-29 16:14:38 -07:00 |
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tangxifan
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a3e7133d63
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Merge branch 'master' into wire_lut_test
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2022-09-29 16:02:18 -07:00 |