85089cbc88
[arch] apply xml format for all the architecture files
2022-10-07 10:31:51 -07:00
a6c7bb2c48
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
019208ec0f
[Architecture] Reorganize the cell netlists and update architecture files accordingly
2020-09-25 11:55:28 -06:00
4a0a448171
[Architecture] Rename openfpga architecture for the I/O cell
2020-09-24 19:56:01 -06:00
0a5369f919
[Architecture] Adapt all the architecture files to use standard DFF cell
2020-09-24 17:26:48 -06:00
2add0406a7
[Architecture] Update architecture files for new latch naming
2020-09-24 12:14:03 -06:00
906191e931
[Architecture] Use strict latch Verilog HDL in frame-based procotol
2020-09-23 17:58:13 -06:00
1c5bede282
update arch file with device technology binding information
2020-07-13 19:06:51 -06:00
60dd37e086
remove simulation settings from openfpga arch XML
...
update travis to split CI tests
fix errors in travis configuration
fixing travis errors in scripts
keep fixing travis
fix travis on build.sh
bug fixing in travis CI
bug fix in travis regression test run
fixing bugs in the travis scripts
bug fix in travis script: remove common.sh in regression test call
keep bug fixing in travis
2020-06-11 19:31:17 -06:00
6a72c66eb8
bug fixed for frame-based configuration memory in top-level full testbench
2020-06-11 19:31:11 -06:00
3fa3b17061
start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
2020-06-11 19:31:10 -06:00
tangxifan