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OpenFPGA
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3 Commits

Author SHA1 Message Date
tangxifan 56113e1aab adding XML parsing for design tech of circuit model 2020-01-14 14:10:00 -07:00
tangxifan 2692d0fc35 adding XML parsing for SPICE and Verilog netlist for each circuit model 2020-01-14 08:45:27 -07:00
tangxifan 82d83ddceb reorganized the read XML openfpga arch 2020-01-14 08:33:48 -07:00