tangxifan
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46510388be
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[core] now fabric generator can wire clock ports to routing blocks
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2023-03-02 12:33:26 -08:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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0c329866da
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[engine] Use RRGraphView in openfpga source codes
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2022-08-16 16:48:32 -07:00 |
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tangxifan
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2c5634ee76
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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tangxifan
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9cbc374b33
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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tangxifan
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cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
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2020-11-10 16:59:00 -07:00 |
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tangxifan
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9dc9c2c9f7
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add build top module connection functions
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2020-02-14 10:45:24 -07:00 |