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OpenFPGA
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2 Commits

Author SHA1 Message Date
tangxifan 53da5d49fe [Arch] Correct XML syntax errors 2021-09-22 15:48:14 -07:00
tangxifan 3cfd5c3531 [Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks 2021-09-22 15:04:59 -07:00