Commit Graph

8055 Commits

Author SHA1 Message Date
Lin 5174b7a336 add capnp for unique blocks and add write bin function 2024-09-26 17:39:52 +08:00
Lin faa222f2c1 create capnp folder 2024-09-25 18:42:04 +08:00
tangxifan 4af766930b
Merge pull request #1846 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2024-09-24 05:42:21 -07:00
github-actions[bot] 1c70b797f8 Updated Patch Count 2024-09-24 09:56:27 +00:00
tangxifan 5072872a82
Merge pull request #1845 from lnis-uofu/dependabot/submodules/yosys-8e1e2b9
Bump yosys from `4d581a9` to `8e1e2b9`
2024-09-24 02:56:06 -07:00
dependabot[bot] 9b7583ff51
Bump yosys from `4d581a9` to `8e1e2b9`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `4d581a9` to `8e1e2b9`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](4d581a97d6...8e1e2b9a39)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
2024-09-24 06:44:52 +00:00
tangxifan ece9fc0eb8
Merge pull request #1844 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2024-09-21 23:35:40 -07:00
github-actions[bot] 1ce23c425f Updated Patch Count 2024-09-22 06:34:46 +00:00
tangxifan 41cf56e372
Merge pull request #1843 from lnis-uofu/xt_clkmux
Support intermediate drivers in programmable clock network
2024-09-21 23:34:25 -07:00
tangxifan c52610959c [core] code format 2024-09-21 21:54:37 -07:00
tangxifan f009180bbf [core] refactor 2024-09-21 21:53:53 -07:00
tangxifan 415fd9a8fa [core] code format 2024-09-21 21:39:30 -07:00
tangxifan 9e461284d0 [core] standardize API for clock network intermeidate drivers 2024-09-21 21:38:32 -07:00
tangxifan af09120a52 [doc] update fig 2024-09-21 13:35:42 -07:00
tangxifan 26cda624d3 [doc] add new syntax about clock network 2024-09-21 13:31:30 -07:00
tangxifan 4e85a6f414 [core] code format 2024-09-20 22:37:05 -07:00
tangxifan 33a253da3d [core] fixed the bug 2024-09-20 22:20:41 -07:00
tangxifan 6551ca81e5 [core] debugging 2024-09-20 19:48:02 -07:00
tangxifan 6d3d36626e [test] typo 2024-09-20 19:29:47 -07:00
tangxifan ed33b62a60 [test] add new tests to validate intermediate drivers in clock 2024-09-20 19:27:40 -07:00
tangxifan 2bb87ea278 [core] code format 2024-09-20 19:23:14 -07:00
tangxifan f87e095558 [core] support intermediate driver in clock routing 2024-09-20 19:22:39 -07:00
tangxifan e8957b6fd8 [core] enable clock intermediate driver in rrgraph buildup 2024-09-20 19:07:16 -07:00
tangxifan 1332d426c7 [core] code format 2024-09-20 17:42:53 -07:00
tangxifan 965ee2190e [core] support intermediate driver in clock arch 2024-09-20 17:42:26 -07:00
tangxifan 9a9d684f58
Merge pull request #1842 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2024-09-19 12:12:56 -07:00
github-actions[bot] fcb151d0f4 Updated Patch Count 2024-09-19 18:43:09 +00:00
tangxifan 0c43e99d39
Merge pull request #1841 from lnis-uofu/xt_mux
Support last stage pass-gate-logic model for MUX circuit model
2024-09-19 11:42:50 -07:00
tangxifan 4905e694ab [doc] typo 2024-09-18 21:59:06 -07:00
tangxifan 8e04d473f2 [core] code format 2024-09-18 21:10:31 -07:00
tangxifan 44a07704ff [core] add check codes for last stage pgl model 2024-09-18 21:10:02 -07:00
tangxifan 1789ce06c4 [doc] update new syntax with example 2024-09-18 17:55:05 -07:00
tangxifan f6b645fd25 [core] code format 2024-09-18 17:44:55 -07:00
tangxifan 1673d9b919 [core] fixed a bug 2024-09-18 17:43:41 -07:00
tangxifan 7b4f06ed7d [test] validate mux2 at last stage 2024-09-18 17:40:13 -07:00
tangxifan 82878063c1 [core] syntax 2024-09-18 17:32:04 -07:00
tangxifan 47e30c3e4b [core] support last stage mux 2024-09-18 17:26:44 -07:00
tangxifan b350889ab3
Merge pull request #1839 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2024-09-18 09:22:17 -07:00
github-actions[bot] 415629429c Updated Patch Count 2024-09-18 16:21:20 +00:00
tangxifan 5db0fde61f
Merge pull request #1838 from lnis-uofu/dependabot/submodules/yosys-4d581a9
Bump yosys from `c884624` to `4d581a9`
2024-09-18 09:20:58 -07:00
dependabot[bot] be72c42f25
Bump yosys from `c884624` to `4d581a9`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `c884624` to `4d581a9`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](c8846243c2...4d581a97d6)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
2024-09-18 06:51:18 +00:00
tangxifan 95cfc57f2f
Merge pull request #1837 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2024-09-17 12:54:34 -07:00
github-actions[bot] f3f9028c24 Updated Patch Count 2024-09-17 19:54:19 +00:00
tangxifan 4066addec4
Merge pull request #1836 from lnis-uofu/dependabot/submodules/yosys-c884624
Bump yosys from `c8b42b7` to `c884624`
2024-09-17 12:53:59 -07:00
dependabot[bot] 337db13f17
Bump yosys from `c8b42b7` to `c884624`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `c8b42b7` to `c884624`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](c8b42b7d48...c8846243c2)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
2024-09-17 06:10:29 +00:00
tangxifan 03b06ba5e5
Merge pull request #1810 from lnis-uofu/preloading_clean
Preloading clean
2024-09-16 12:13:25 -07:00
Jingrong Lin b5452b7a3c
Merge branch 'master' into preloading_clean 2024-09-14 10:54:14 +08:00
tangxifan 9077ee0ef4
Merge pull request #1835 from lnis-uofu/patch_update
Pulling refs/heads/master into master
2024-09-13 10:30:05 -07:00
github-actions[bot] e439acf5fc Updated Patch Count 2024-09-13 17:28:43 +00:00
tangxifan 88057066e3
Merge pull request #1834 from lnis-uofu/dependabot/submodules/yosys-c8b42b7
Bump yosys from `229d1ea` to `c8b42b7`
2024-09-13 10:28:25 -07:00