4 Commits

Author	SHA1	Message	Date
tangxifan	512e9f4e8e	refactoring Verilog generation for primitive pb_types	2019-10-08 12:10:26 -06:00
tangxifan	173b886314	add module name generation for pb_types	2019-10-07 21:09:54 -06:00
tangxifan	86c9af872e	refactoring physical block Verilog generation	2019-10-07 17:39:00 -06:00
tangxifan	997bfdbb95	move the refactored function for physical block Verilog generation to a new source file	2019-10-07 16:03:15 -06:00