4 Commits

Author	SHA1	Message	Date
Lalit Sharma	ea4aee8cb2	For time-being yosys script running in no_adder mode.	2021-02-28 22:07:23 -08:00
Lalit Sharma	d842026672	Disabling verilog testbench generation for quicklogic tests	2021-02-21 21:58:23 -08:00
Tarachand Pagarani	426b6449d8	change the test to turn off power analysis	2021-02-15 02:45:38 -08:00
Lalit Sharma	2484721a45	Updating write_verilog_testbench by removing option explicit_port_mapping	2020-12-22 22:17:50 -08:00