4 Commits

Author	SHA1	Message	Date
BaudouinChauviere	88af64c606	Update eda_flow.rst ... Distributions compilable added	2018-12-05 16:29:07 -07:00
BaudouinChauviere	576feb600f	Update eda_flow.rst ... Completed with FPGA-Verilog/Bitstream and corrected few errors	2018-12-05 16:24:03 -07:00
唐希凡	0bfbc9b0aa	update docs	2018-09-14 13:11:51 -06:00
Xifan Tang	fec0daa2a8	Update a draft	2018-09-13 22:58:54 -06:00