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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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3 Commits
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tangxifan
910be3cadb
massively deploy disable_timing for configure ports in CI
2020-06-11 19:31:06 -06:00
tangxifan
1943929353
add write_fabric_hierarchy to regression tests
2020-06-11 19:31:04 -06:00
tangxifan
59ea0a6ad5
add implicit verilog test case to Travis CI
2020-04-12 20:00:20 -06:00