tangxifan
|
15f087598c
|
split simulation settings to a separated XML file
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
8267dad8ef
|
add decoder support for Z signals
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
b8c449d520
|
add comments for decoding functions to help debugging the frame-based decoders
|
2020-06-11 19:31:11 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a26bb5eef
|
add advanced check in configurable memories
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
62c506182c
|
start developing frame-based configuration protocol
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
f52b5d5b4c
|
use error code in read_arch command
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
05d276097e
|
critical bug fixed in openfpga shell so that our command parse results should be reset each time before parsing a line
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
6aff33dd35
|
add fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
8726c618eb
|
add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
8695c5ee78
|
add options to use general-purpose wildcards in SDC generator
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
|
2020-04-22 14:41:16 -06:00 |
|
tangxifan
|
07a384e440
|
now use openfpga tokenizer to trim command line string in openfpga shell
|
2020-04-13 11:08:31 -06:00 |
|
tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
tangxifan
|
b9dab2baaf
|
add exit codes to command execution in shell context
|
2020-04-08 16:18:05 -06:00 |
|
tangxifan
|
1fb37f4c71
|
improve directory creator to support same functionality as 'mkdir -p'
|
2020-04-08 12:55:09 -06:00 |
|
tangxifan
|
e31dc1f2f2
|
openfpga shell now support continued line charactor '\'
|
2020-04-07 21:27:51 -06:00 |
|
tangxifan
|
33315f0521
|
now openfpga shell allow empty space at beginning and end of each line in script mode
|
2020-04-07 20:46:45 -06:00 |
|
tangxifan
|
6eb125ec2a
|
Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
|
2020-04-06 14:09:52 -06:00 |
|
tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
|
2020-04-05 16:01:25 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
|
2020-03-27 20:09:50 -06:00 |
|
tangxifan
|
3647548526
|
clean up on the shell echo commands
|
2020-03-20 11:07:45 -06:00 |
|
tangxifan
|
3aca7b498c
|
Show help desk when a command is called inside shell without satisfying the dependency
|
2020-03-09 09:34:21 -06:00 |
|
tangxifan
|
b035b4c87f
|
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
|
2020-02-21 12:16:50 -07:00 |
|
tangxifan
|
c6c3ef71f3
|
adapt all the Verilog submodule writers and bring it onlien
|
2020-02-16 13:35:18 -07:00 |
|
tangxifan
|
a88c4bc954
|
add decode utils to libopenfpga and adapt local decoder writer in Verilog
|
2020-02-16 12:21:59 -07:00 |
|
tangxifan
|
622c7826d1
|
start transplanting fpga_verilog
|
2020-02-15 15:03:00 -07:00 |
|
tangxifan
|
59c13550e0
|
add direct annotation with inter-column/row syntax
|
2020-02-14 17:40:59 -07:00 |
|
tangxifan
|
df3ae60954
|
add default configurable memory model set-up when reading openfpga architecture XML
|
2020-02-12 15:19:40 -07:00 |
|
tangxifan
|
99f5a86b49
|
bug fixed for routing annotation and routing net fix-up
|
2020-02-06 12:54:55 -07:00 |
|
tangxifan
|
87f1ca1151
|
add naming fix-up report generation
|
2020-01-29 18:56:47 -07:00 |
|
tangxifan
|
24b180b298
|
change the mode bit storage in annotation data structure from string to vector of integers
|
2020-01-29 11:59:20 -07:00 |
|
tangxifan
|
df056f5d70
|
openfpga shell will stay in interactive mode after executing a script
|
2020-01-27 17:56:24 -07:00 |
|
tangxifan
|
5ecb771673
|
debugging the annotation to physical mode of pb_types
|
2020-01-27 17:43:22 -07:00 |
|
tangxifan
|
7d4b07421d
|
finish XML parser and writer for pb_type annotation
|
2020-01-26 15:54:49 -07:00 |
|
tangxifan
|
1cba141dd0
|
add pb parser and support XML parsing for pb type name in full hiearchy
|
2020-01-26 11:52:58 -07:00 |
|
tangxifan
|
cd3565cf53
|
complete the XML parser for pb_type annotation
|
2020-01-26 10:56:57 -07:00 |
|
tangxifan
|
a9f03ce21b
|
add XML attribute parsing for physical and operating pb_type annotation
|
2020-01-26 10:19:47 -07:00 |
|
tangxifan
|
bafd866cfc
|
start developing XML parser for pb_type annotation
|
2020-01-25 21:19:08 -07:00 |
|
tangxifan
|
b6f96e5a8f
|
add method functions to pb_type annotation
|
2020-01-25 20:46:21 -07:00 |
|
tangxifan
|
9b4b6ae083
|
rename pb_annotation and move it to openfpga namespace
|
2020-01-25 18:17:00 -07:00 |
|
tangxifan
|
f834954698
|
start developing the pb_type annotation
|
2020-01-25 18:14:38 -07:00 |
|
tangxifan
|
b4f4bf62a2
|
add comments to sample arch
|
2020-01-25 17:42:24 -07:00 |
|
tangxifan
|
7feeee8c0e
|
add full syntax to sample_arch.xml about the physical pb_type binding
|
2020-01-25 17:38:06 -07:00 |
|
tangxifan
|
b641ae15d3
|
add command dependency in shell execution
|
2020-01-24 16:46:39 -07:00 |
|
tangxifan
|
655f84b00e
|
add write_openfpga_arch command to openfpga shell
|
2020-01-23 20:58:15 -07:00 |
|
tangxifan
|
a03f8aa346
|
add profiling for read arch
|
2020-01-23 20:12:30 -07:00 |
|
tangxifan
|
cdb3b6de46
|
add read_openfpga_arch to OpenFPGA shell
|
2020-01-23 19:10:53 -07:00 |