4 Commits

Author	SHA1	Message	Date
tangxifan	4c04c0fbd7	[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models	2021-09-28 12:35:42 -07:00
tangxifan	a98df811ed	[Arch] Bug fix: wrong circuit model name was used for CCFF	2021-09-22 15:50:47 -07:00
tangxifan	53da5d49fe	[Arch] Correct XML syntax errors	2021-09-22 15:48:14 -07:00
tangxifan	3cfd5c3531	[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks	2021-09-22 15:04:59 -07:00